RF acoustic wave resonators integrated with high electron mobility transistors including a shared piezoelectric/buffer layer and methods of forming the same
An RF integrated circuit device can includes a substrate and a High Electron Mobility Transistor (HEMT) device on the substrate including a ScAlN layer configured to provide a buffer layer of the HEMT device to confine formation of a 2DEG channel region of the HEMT device. An RF piezoelectric resonator device can be on the substrate including the ScAlN layer sandwiched between a top electrode and a bottom electrode of the RF piezoelectric resonator device to provide a piezoelectric resonator for the RF piezoelectric resonator device.
1. An RF integrated circuit device comprising:
a substrate;
a High Electron Mobility Transistor (HEMT) device on the substrate including a ScAlN layer configured to provide a buffer layer of the HEMT device to confine formation of a 2DEG channel region of the HEMT device; and
an RF piezoelectric resonator device on the substrate including the ScAlN layer sandwiched between a top electrode and a bottom electrode of the RF piezoelectric resonator device to provide a piezoelectric resonator for the RF piezoelectric resonator device.
2. The RF integrated circuit device of claim 1 further comprising:
an RF piezoelectric resonator cavity between the bottom electrode and the substrate.
3. The RF integrated circuit device of claim 1 wherein the HEMT device further comprises:
a GaN channel layer on the ScAlN layer;
a barrier layer on the GaN channel layer to provide the 2DEG channel region in the GaN channel layer;
a GaN drain region recessed into the GaN channel layer at a first end of the 2DEG channel region;
a GaN source region recessed into the GaN channel layer at a second end of the 2DEG channel region opposite the first end of the 2DEG channel region; and
a gate electrode between the GaN drain region and the GaN source region opposite the barrier layer and configured to modulate the 2DEG channel region in the GaN channel layer.
4. The RF integrated circuit device of claim 1 wherein the ScAlN layer is stress-balanced relative to a GaN channel layer of the HEMT device located on the ScAlN layer.
5. The RF integrated circuit device of claim 4 wherein the ScAlN layer comprises Sc 0.18 Al 0.82 N.
6. The RF integrated circuit device of claim 4 wherein the HEMT device further comprises:
a GaN channel layer on the ScAlN layer; and
a ScAlN barrier layer on the GaN channel layer to provide the 2DEG channel region in the GaN channel layer.
7. The RF integrated circuit device of claim 4 wherein the HEMT device further comprises:
a GaN channel layer on the ScAlN layer; and
a AlGaN barrier layer on the GaN channel layer to provide the 2DEG channel region in the GaN channel layer.
8. The RF integrated circuit device of claim 4 wherein the HEMT device further comprises:
a GaN channel layer on the ScAlN layer;
an AlN sub-barrier layer on the GaN channel layer; and
a barrier layer including AlN on the AlN sub-barrier layer to provide the 2DEG channel region in the GaN channel layer.
9. The RF integrated circuit device of claim 1 wherein the ScAlN layer comprises a single crystal ScAlN material.
10. The RF integrated circuit device of claim 9 wherein the single crystal ScAlN material has a crystalline structure characterized by an XRD rocking curve FWHM value in a range between about less than 1.0 degrees to about 0.001 degrees as measured about a two-theta ( 2 Θ) scan angle.
11. The RF integrated circuit device of claim 1 wherein the substrate comprises a silicon <100> substrate.
12. The RF integrated circuit device of claim 1 wherein the ScAlN layer comprises Sc 0.18 Al 0.82 N layer having a thickness of about 2 microns to about 0.01 microns, the HEMT device further comprising:
a GaN channel layer on the Sc 0.18 Al 0.82 N layer, the GaN channel layer having a thickness of about 0.1 microns to about 1.0 micron; and
a ScAlN barrier layer on the GaN channel layer, the ScAlN barrier layer having a thickness of about 200 nm to about 0.01 microns.
13. The RF integrated circuit device of claim 3 further comprising:
a GaN or SiN passivation layer between the gate electrode and the barrier layer.
14. The RF integrated circuit device of claim 3 further comprising:
a passivation layer grown directly on the barrier layer.