Stacked memory structure with insulating patterns

1. A semiconductor device, comprising:

a stacked structure with insulating layers and conductive layers that are alternately stacked on each other, wherein the insulating layers and the conductive layers extend in a first direction;

a hard mask pattern on the stacked structure;

a channel structure extending in a second direction perpendicular to the hard mask pattern and the stacked structure;

insulating patterns interposed between the insulating layers and the channel structure and interposed between the conductive layers spaced apart in the second direction, wherein the insulating patterns protrude farther towards the channel structure than a sidewall of the hard mask pattern; and

a memory layer interposed between the stacked structure and the channel structure, wherein the memory layer fills a space between the insulating patterns.

2. The semiconductor device of claim 1 , wherein the insulating patterns and the insulating layers have different properties of matter.

3. The semiconductor device of claim 1 , wherein each of the insulating patterns includes a first surface that faces each of the insulating layers and a second surface that faces the channel structure, and

wherein each of the first surface and the second surface includes a curved surface.

4. The semiconductor device of claim 1 , wherein each of the insulating patterns includes a first surface that faces each of the insulating layers and a second surface that faces the channel structure, and

wherein the first surface includes a curved surface and the second surface includes a plane.

5. The semiconductor device of claim 1 , wherein each of the insulating patterns includes a first portion, interposed between the conductive layers and a second portion, protruding farther than a sidewall of each of the conductive layers.

6. The semiconductor device of claim 5 , wherein the second portion has a greater width than the first portion.

7. The semiconductor device of claim 5 , wherein the second portion has substantially a same width as the first portion.

8. The semiconductor device of claim 5 , wherein the second portion has a smaller width than the first portion.

9. The semiconductor device of claim 5 , wherein a width of each of second portions of the insulating patterns is different from a width of each of the insulating layers.

10. The semiconductor device of claim 1 , wherein the memory layer includes a data storage layer that surrounds a sidewall of the channel structure, extending to the sidewall of the hard mask pattern, and

wherein the memory layer includes protrusions that protrude between the insulating patterns.

11. The semiconductor device of claim 1 , wherein the memory layer comprises:

first data storage patterns located between the insulating patterns and separated from each other; and

a second data storage pattern extending to the sidewall of the hard mask pattern.

12. The semiconductor device of claim 1 , wherein a sidewall of each of the conductive layers is located on an extending line of the sidewall of the hard mask pattern.

13. The semiconductor device of claim 1 , wherein an interface between each of the insulating layers and each of the insulating patterns is located to be spaced apart farther from a sidewall of the channel structure than the sidewall of the hard mask pattern.

14. The semiconductor device of claim 1 , wherein interfaces between the insulating layers and the insulating patterns are convex towards the insulating layers.