IP Library Granted Patent US 11,250,981
Granted Patent B2
US 11,250,981 · App. 16/993,152 · Granted Feb 15, 2022

Vertical inductor for WLCSP

Inventors: Andreas Wolter (Regensburg, DE); Thorsten Meyer (Regensburg, DE); Gerhard Knoblinger (Villach, AT)
Assignee: Intel Corporation
H01F17/0033H01F41/046H01L23/5227H01L23/645H01L24/17H01F2017/0086H01F2027/2814H01L24/13H01L24/16H01L2224/0345H01L2224/03462H01L2224/03464H01L2224/0401H01L2224/05647H01L2224/11H01L2224/1132H01L2224/11334H01L2224/11462H01L2224/16265H01L2224/16267H01L2224/171H01L2224/1703H01L2924/19042H01L2924/19104H01L2924/19107
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Quick Facts
Patent No.
US 11,250,981
App. No.
16/993,152
Granted
Feb 15, 2022
Kind
B2
Abstract

Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

Claims (9)

1. A microelectronic device, comprising:

a semiconductor die; and

an inductor electrically coupled to the semiconductor die, wherein the inductor includes one or more conductive coils that extend away from a surface of the semiconductor die, wherein the inductor comprises a dielectric layer having a first via and a second via therein, the first via and the second via electrically coupled to each other with a conductive trace, and wherein the inductor is electrically coupled to the semiconductor die with solder balls.

2. The microelectronic device of claim 1 , wherein the first via and the second via are electrically coupled to the solder balls.

3. The microelectronic device of claim 2 , wherein the solder balls are coupled to a first redistribution line and a second redistribution line formed on the semiconductor die.

4. The microelectronic device of claim 1 , wherein the inductor comprises a first redistribution line coupled to the first via and a second redistribution line coupled to the second via, wherein each of the first and second redistribution lines are formed on a surface of the inductor substrate opposite the surface the conductive trace, and wherein the first and second redistribution lines are electrically coupled to the solder balls.

5. A microelectronic device, comprising:

a semiconductor die; and

an inductor electrically coupled to the semiconductor die, wherein the inductor includes one or more conductive coils that extend away from a surface of the semiconductor die, wherein the inductor is electrically coupled to the semiconductor die with solder balls, wherein the inductor comprises a dielectric layer having a first via and a second via electrically coupled to each other with a conductive trace, and a first redistribution line coupled to the first via and a second redistribution line coupled to the second via, wherein each of the first and second redistribution lines are formed on a surface of the inductor substrate opposite the surface the conductive trace, and wherein the first and second redistribution lines are electrically coupled to the solder balls.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2021
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 056524/0373 →