Method of using multidimensional blockification to optimize computer program and device thereof
Disclosed embodiments relate to a method and device for optimizing compilation of source code. The proposed method receives a first intermediate representation code of a source code and analyses each basic block instruction of the plurality of basic block instructions contained in the first intermediate representation code for blockification. In order to blockify the identical instructions, the one or more groups of basic block instructions are assessed for eligibility of blockification. Upon determining as eligible, the group of basic block instructions are blockified using one of one dimensional SIMD vectorization and two-dimensional SIMD vectorization. The method further generates a second intermediate representation of the source code which is translated to executable target code with more efficient processing capacity.
1. A computer implemented method for enhancing compilation of source code, the method comprising:
receiving a first intermediate representation code of the source code as input data, wherein the first intermediate representation code comprises a plurality of basic block (BB) instructions generated from the corresponding source code;
analyzing each of the plurality of BB instructions to determine one or more groups of identical BB instructions that satisfy at least one criteria for blockification, comprising identifying a minimum offset and a maximum offset for each group of identical BB instructions, wherein each group of identical BB instructions is identified based on instruction identifier and allotted buffer, computing an area for each group of identical BB instructions based on the minimum offset and the maximum offset identified, and determining that each group of identical BB instructions satisfies the criteria for blockification when a difference between the computed area and a total number of identical BB instructions in each group is less than a threshold;
generating, based on the determination, a second intermediate representation code by blockification of at least one of one or more groups of identical BB instructions in the first intermediate representation code; and
compiling the second intermediate representation code to obtain a corresponding enhanced executable code for executing the source code.
2. The computer implemented method of claim 1 , wherein the step of blockification comprises merging of the at least one of one or more groups of identical BB instructions using one of one-dimensional Single Instruction Multiple Data (SIMD) vectorization and two-dimensional SIMD vectorization.
3. The computer implemented method of claim 2 , wherein merging the at least one of one or more groups of identical BB instructions comprises generating one or more vector instructions for each group of identical instructions using one of one-dimensional SIMD vectorization and two-dimensional SIMD vectorization.
4. The computer implemented method of claim 3 , wherein generating the one or more vector instructions comprises generating the one or more vector instructions based on SIMD width of a vector register.
5. The computer implemented method of claim 1 , wherein each BB instruction is one of LOAD, Arithmetic Logic and Multiply (ALM), and STORE instructions, wherein the instruction identifier is at least one of LOAD, ALM, and STORE identifier.
6. A device to enhance compilation of source code, the device comprising:
a memory;
a processor, coupled to the memory, and configured to:
receive a first intermediate representation n code of the source code as input data, wherein the first intermediate representation code comprises a plurality of basic block (BB) instructions generated from the corresponding source code;
analyze each of the plurality of BB instructions to determine one or more groups of identical BB instructions that satisfy at least one criteria for blockification, comprising the processor being configured to identify a minimum offset and a maximum offset for each group of identical BB instructions, wherein each group of identical BB instructions is identified based on instruction identifier and allotted buffer, compute an area for each group of identical BB instructions based on the minimum offset and the maximum offset identified, and determine that each group of identical BB instructions satisfies the criteria for blockification when a difference between the computed area and a total number of identical BB instructions in each group is less than a threshold;
generate, based on the determination, a second intermediate representation code by blockification of at least one of one or more groups of identical BB instructions in the first intermediate representation code; and
compile the second intermediate representation code to obtain a corresponding enhanced executable code for executing the source code.
7. The device of claim 6 , wherein the step of blockification includes merge the at least one of one or more groups of identical BB instructions using one of one-dimensional Single Instruction Multiple Data (SIMD) vectorization and two-dimensional SIMD vectorization.
8. The device of claim 7 , wherein to merge the at least one of one or more groups of identical BB instructions, the processor is configured to generate one or more vector instruction for each group of identical instructions using one of one-dimensional single instruction multiple data (SIMD) vectorization and two-dimensional SIMD vectorization.
9. The processing device of claim 8 , wherein the generation of the one or more vector instructions comprises generate the one or more vector instructions based on SIMD width of a vector register.
10. The processing device of claim 6 , wherein each BB instructions is one of LOAD, Arithmetic Logic Multiply (ALM), and STORE instructions.
11. A non-transitory computer-readable storage medium that stores instructions executable by a computer that, in response to execution by the computer, cause the computer to perform or control performance of operations comprising:
receive a first intermediate representation code of the source code as input data, wherein the first intermediate representation code comprises a plurality of basic block (BB) instructions generated from the corresponding source code;
analyze each of the plurality of BB instructions to determine one or more groups of identical BB instructions that satisfy at least one criteria for blockification, comprising identifying a minimum offset and a maximum offset for each group of identical BB instructions, wherein each group of identical BB is identified based on instruction identifier and allotted buffer, computing an area for each group of identical BB instructions based on the minimum offset and the maximum offset identified, and determining that each group of identical BB instructions satisfies the criteria for blockification when a difference between the computed area and a total number of identical BB instructions in each group is less than a threshold;
generate, based on the determination, a second intermediate representation code by blockification of at least one of one or more groups of identical BB instructions in the first intermediate representation code; and
compile the second intermediate representation code to obtain a corresponding enhanced executable code for executing the source code.
12. The non-transitory computer-readable storage medium of claim 11 , wherein the operations for blockification comprises at least one operation to merge the at least one of one or more groups of identical BB instructions using one of one-dimensional single instruction multiple data (SIMD) vectorization and two-dimensional SIMD vectorization.
13. The non-transitory computer-readable storage medium of claim 12 , wherein the operations to merge the at least one of one or more groups of identical BB instructions comprises at least one operations to generate one or more vector instructions by converting each group of identical instructions using one of one-dimensional SIMD vectorization and two-dimensional SIMD vectorization.
14. The non-transitory computer-readable storage medium of claim 13 , wherein the operation to generate the one or more vector instructions comprises generating one or more vector instructions based on SIMD width of a vector register.
15. The non-transitory computer-readable storage medium of claim 11 , wherein each BB instruction is one of LOAD, Arithmetic Logic Multiply (ALM), and STORE instructions.