Hybrid analog-digital matrix processors
Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.
1. A hybrid analog-digital processor comprising:
a digital-to-analog converter (DAC) unit comprising a plurality of DACs;
a photonic processor arranged to perform matrix-matrix multiplication or matrix-vector multiplication and coupled to outputs of the DAC unit;
an analog-to-digital (ADC) unit comprising a plurality of ADCs and coupled to outputs of the photonic processor;
a digital multiplicative scaling unit coupled to outputs of the ADC unit; and
a digital accumulator coupled to outputs of the digital multiplicative scaling unit, wherein the digital accumulator comprises a memory unit and a digital adder.
2. The hybrid analog-digital processor of claim 1 , further comprising an optical amplification or attenuation unit coupled between the DAC unit and the ADC unit.
3. The hybrid analog-digital processor of claim 1 , wherein the photonic processor comprises a plurality of Mach-Zehnder interferometers.
4. The hybrid analog-digital processor of claim 1 , wherein the photonic processor comprises a plurality of nano-opto-electromechanical switches (NOEMS).
5. The hybrid analog-digital processor of claim 1 , wherein the photonic processor comprises a plurality of Franz-Keldysh modulators.
6. The hybrid analog-digital processor of claim 1 , wherein the photonic processor comprises:
a first array of interconnected variable beam splitters (VBSs) comprising a first plurality of optical inputs and a first plurality of optical outputs;
a second array of interconnected VBSs comprising a second plurality of optical inputs and a second plurality of optical outputs; and
a plurality of controllable optical elements, each of the plurality of these controllable optical elements coupling a single one of the first plurality of optical outputs of the first array to a respective single one of the second plurality of optical inputs of the second array.
7. The hybrid analog-digital processor of claim 1 , wherein the photonic processor is programmed with a plurality of matrices that, collectively, represent an arbitrary matrix.
8. The hybrid analog-digital processor of claim 1 , wherein the digital multiplicative scaling unit is configured to perform divisions.
9. A hybrid analog-digital processor comprising:
a digital-to-analog converter (DAC) unit comprising a plurality of DACs;
an analog processor arranged to perform matrix-matrix multiplication or matrix-vector multiplication and coupled to outputs of the DAC unit;
an analog-to-digital (ADC) unit comprising a plurality of ADCs and coupled to outputs of the analog processor;
a digital multiplicative scaling unit coupled to outputs of the ADC unit; and
a digital accumulator coupled to outputs of the digital multiplicative scaling unit, wherein the digital accumulator comprises a memory unit and a digital adder.
10. The hybrid analog-digital processor of claim 9 , wherein the analog processor comprises a plurality of analog mixers.
11. The hybrid analog-digital processor of claim 9 , wherein the analog processor comprises a plurality of programmable analog amplifiers or attenuators.
12. The hybrid analog-digital processor of claim 9 , wherein the analog processor comprises a plurality of memory devices arranged in a crossbar configuration.
13. The hybrid analog-digital processor of claim 12 , wherein the plurality of memory devices arranged in the crossbar configuration comprise a plurality of flash memory cells.
14. The hybrid analog-digital processor of claim 9 , wherein the plurality of ADCs are n-bit ADCs, where n is less than or equal to 12.
15. The hybrid analog-digital processor of claim 9 , further comprising an analog amplification or attenuation unit coupled between the DAC unit and the ADC unit.
16. The hybrid analog-digital processor of claim 9 , wherein the analog processor is programmed with a plurality of matrices that, collectively, represent an arbitrary matrix based on a singular value decomposition (SVD).
17. The hybrid analog-digital processor of claim 9 , wherein the analog processor is programmed with a plurality of matrices that, collectively, represent an arbitrary matrix based on a dilation.
18. The hybrid analog-digital processor of claim 9 , wherein the digital multiplicative scaling unit is configured to perform divisions.
19. A method of manufacturing a hybrid analog-digital processor comprising:
forming a digital-to-analog converter (DAC) unit comprising a plurality of DACs;
forming an analog processor arranged to perform matrix-matrix multiplication or matrix-vector multiplication and coupled to outputs of the DAC unit;
forming an analog-to-digital (ADC) unit comprising a plurality of ADCs and coupled to outputs of the analog processor;
forming a digital multiplicative scaling unit coupled to outputs of the ADC unit; and
forming a digital accumulator coupled to outputs of the digital multiplicative scaling unit, wherein the digital accumulator comprises a memory unit and a digital adder.
20. The method of claim 19 , wherein forming the analog processor comprises forming a photonic processor arranged to perform the matrix-matrix multiplication or the matrix-vector multiplication optically, and wherein the ADC unit is coupled to the outputs of the photonic processor.
21. The method of claim 20 , wherein forming the photonic processor and forming the digital accumulator comprises forming the photonic processor and the digital accumulator on a common chip.
22. The method of claim 19 , wherein forming the photonic processor and forming the digital accumulator comprises:
forming the photonic processor on a first chip;
forming the digital accumulator on a second chip; and
bonding the first chip to the second chip.
23. The method of claim 19 , wherein the digital multiplicative scaling unit is configured to perform divisions.