Sub-wordline driver
A sub-wordline driver for a semiconductor memory device is disclosed. The sub-wordline driver includes a selection controller and a plurality of driving circuits. The selection controller selectively outputs any one of a first-group wordline selection signal and a second-group wordline selection signal in response to a selection signal and a wordline drive signal. The plurality of driving circuits selectively output any one of a plurality of sub-wordline drive signals in response to a main wordline drive signal, the wordline drive signal, the first-group wordline selection signal, and the second-group wordline selection signal.
1. A sub-wordline driver comprising:
a selection controller configured to selectively output any one of a first-group wordline selection signal and a second-group wordline selection signal in response to a selection signal and a wordline drive signal; and
a plurality of driving circuits configured to selectively output any one of a plurality of sub-wordline drive signals in response to a main wordline drive signal, the wordline drive signal, one of the first-group wordline selection signal and the second-group wordline selection signal.
2. The sub-wordline driver according to claim 1 , wherein:
the selection controller is configured to activate the first-group wordline selection signal when the selection signal and the wordline drive signal are at a first logic level; and
the selection controller is configured to activate the second-group wordline selection signal when the selection signal is at a second logic level and the wordline drive signal is at the first logic level.
3. The sub-wordline driver according to claim 1 , wherein the selection controller is disposed in a sub-hole region.
4. The sub-wordline driver according to claim 1 , wherein each of the plurality of driving circuits includes:
a first transistor coupled between an input terminal of the first-group wordline selection signal and an output terminal of a first sub-wordline drive signal, and configured to receive the main wordline drive signal through a gate terminal thereof;
a second transistor coupled between an input terminal of the second-group wordline selection signal and an output terminal of a second sub-wordline drive signal, and configured to receive the main wordline drive signal through a gate terminal thereof;
third and fourth transistors coupled in series between the first transistor and the second transistor, and configured to receive the main wordline drive signal through a common gate terminal thereof; and
fifth and sixth transistors coupled in series between the output terminal of the first sub-wordline drive signal and the output terminal of the second sub-wordline drive signal, and configured to receive the wordline drive signal through a common gate terminal thereof.
5. The sub-wordline driver according to claim 4 , wherein each of the first transistor and the second transistor is a PMOS transistor.
6. The sub-wordline driver according to claim 4 , wherein each of the third to sixth transistors is an NMOS transistor.