Lidar system with crosstalk reduction comprising a power supply circuit layer stacked between an avalanche-type diode layer and a read-out circuit layer
A focal-plane array includes an array of pixels. Each pixel includes an avalanche-type diode on a first layer, a read-out circuit (ROIC) on a second layer, and a power-supply circuit on a middle layer stacked between the first layer and the second layer. Since each pixel includes the avalanche-type diode, the ROIC, and the power-supply circuit on different layers circuitry for each pixel is in a top-down footprint of the pixel. Thus a consistent bias voltage to each pixel, decouples the avalanche-type diodes of the different pixels to eliminate crosstalk between adjacent pixels, and allows for individual control of each pixel.
1. A focal-plane array assembly, comprising:
an array of pixels, each pixel including:
an avalanche-type diode on a first layer;
a read-out circuit on a second layer; and
a power-supply circuit on a middle layer stacked between the first layer and the second layer.
2. The focal-plane array as set forth in claim 1 , wherein the array of pixels is a 2-dimensional array.
3. The focal-plane array as set forth in claim 1 , wherein the middle layer is bonded directly to the first layer and the second layer.
4. The focal-plane array as set forth in claim 1 , wherein the avalanche-type diode is an avalanche photodiode.
5. The focal-plane array as set forth in claim 1 , wherein the avalanche-type diode is a single-photon avalanche diode.
6. The focal-plane array as set forth in claim 1 , wherein, for each pixel, the pixel includes a second avalanche-type diode connected to the power-supply circuit of the pixel and connected to the read-out circuit of the pixel.
7. The focal-plane array as set forth in claim 1 , wherein each pixel includes a quenching circuit connected to the avalanche-type diode.
8. The focal-plane array as set forth in claim 1 , further comprising at least one memory chip on the second layer and connected to the read-out circuits, wherein the memory chip is electrically connected to the second layer via wire bonding.
9. A method comprising:
supplying bias voltage to avalanche-type diodes of a plurality of pixels of a focal-plane array through a plurality of power-supply circuits, each power-supply circuit dedicated to one of the pixels;
detecting a photon with at least one of the avalanche-type diodes;
reading out an electrical output of the at least one of the avalanche-type diodes through read-out circuits of the focal-plane array, each read-out circuit of the focal-plane array being dedicated to one of the pixels.
10. The method of claim 9 , wherein the avalanche-type diode is a single-photon avalanche diode, and further comprising quenching the single-photon avalanche diode after detecting the photon.
11. The method of claim 9 , wherein the focal-plane array further includes:
an array of pixels, each pixel including:
at least one avalanche-type diode on a first layer;
a read-out circuit on a second layer; and
a power-supply circuit on a middle layer stacked between the first layer and the second layer.
12. A Lidar system, comprising:
a light emitter; and
a light receiver having a focal-plane array further including:
an array of pixels, each pixel including:
an avalanche-type diode on a first layer;
a read-out circuit on a second layer; and
a power-supply circuit on a middle layer stacked between the first layer and the second layer.
13. The Lidar system as set forth in claim 12 , wherein the light emitter is a Vertical-Cavity Surface-Emitting laser.
14. The Lidar system as set forth in claim 12 , wherein the light emitter is a Diode-Pumped Solid-State laser.
15. The Lidar system as set forth in claim 12 , wherein the light emitter is an Edge-Emitting Laser.
16. The lidar system as set forth in claim 12 , further comprising an optical path having an outer optical facia on a front end and the focal-plane array on a back end, wherein a lens is positioned in the optical path between the front end and the back end.