Granted Patent B2

US 11,431,506 · App. 16/999,495 · Granted Aug 30, 2022

Inventors: Lee Eric Ballard (Georgetown, TX); Jonathan Foster Lewis (Round Rock, TX)

Assignee: Dell Products L.P.

H04L9/3247G06F13/1668G06F13/4282G06F21/602H04L9/0643H04L9/0825H04L9/30G06F2213/0026

Abstract

Claims (96)

1. An information handling system, comprising:

a first bus;

a component that includes a communications bridge, a non-volatile memory medium, a multiplexer, and an integrated circuit; and

a baseboard management controller (BMC);

wherein the component and the BMC are coupled to the first bus;

wherein the BMC includes a processor and a memory medium, coupled to the processor, that stores instructions executable by the processor, which when executed by the processor, cause BMC to:

determine to provide firmware to the component; and

provide first data to the component via a first bus;

wherein the component is configured to:

based at least on the first data, provide, by the communications bridge, a first signal to the non-volatile memory medium, the multiplexer, and the integrated circuit, wherein the first signal causes the integrated circuit to be held in a reset state, causes a write protection of the non-volatile memory medium to be cleared, and causes the multiplexer to couple the BMC to the non-volatile memory medium;

wherein the instructions further cause the BMC to:

provide the firmware to the non-volatile memory medium via the multiplexer;

wherein the component is further configured to:

store, via the non-volatile memory medium, the firmware;

wherein the instructions further cause the BMC to:

provide second data to the component via the first bus; and

wherein the component is further configured to:

based at least on the second data, provide, via the communications bridge, a second signal to the non-volatile memory medium, the multiplexer, and the integrated circuit, wherein the second signal causes the integrated circuit to be released from the reset state, causes the write protection of the non-volatile memory medium to be instated, and causes the multiplexer to couple the non-volatile memory medium to the integrated circuit; and

execute, via the integrated circuit, the firmware.

2. The information handling system of claim 1 ,

wherein the instructions further cause the BMC to:

after the information handling system boots, provide third data to the component via the first bus;

wherein the component is further configured to:

based at least on the third data, provide, via the communications bridge, a third signal to the non-volatile memory medium, the multiplexer, and the integrated circuit, wherein the third signal causes the integrated circuit to be held in the reset state, causes the write protection of the non-volatile memory medium to be cleared, and causes the multiplexer to couple the BMC to the non-volatile memory medium;

wherein the instructions further cause the BMC to:

receive the firmware from the non-volatile memory medium;

determine a first hash value from the firmware;

decrypt a signature associated with the firmware to obtain a second hash value; and

determine that the first hash value matches the second hash value.

3. The information handling system of claim 1 , wherein, to decrypt the signature associated with the firmware to obtain the second hash value, the instructions further cause the BMC to decrypt the signature with a public encryption key.

4. The method of claim 3 , wherein the instructions further cause the BMC to:

obtain the public encryption key from a certificate signed by a certificate authority.

5. The information handling system of claim 1 ,

wherein the communications bridge is coupled to the first bus and is coupled to a second bus;

wherein the multiplexor is coupled to the second bus;

wherein the first bus utilizes a first protocol; and

wherein the second bus utilizes a second protocol, different from the first protocol.

6. The method of claim 5 ,

wherein the first bus includes an inter-integrated circuit bus; and

wherein the second bus includes a serial peripheral interface bus.

7. The information handling system of claim 1 , wherein a Peripheral Component Interconnect Express coupling includes the first bus.

8. A method, comprising:

determining, by a baseboard management controller (BMC) of an information handling system, to provide firmware to a component of the information handling system;

providing, by the BMC, first data to the component via a first bus;

based at least on the first data, providing, by a communications bridge of the component, a first signal to a non-volatile memory medium of the component, a multiplexer of the component, and an integrated circuit of the component, wherein the first signal causes the integrated circuit to be held in a reset state, causes a write protection of the non-volatile memory medium of the component to be cleared, and causes the multiplexer of the component to couple the BMC to the non-volatile memory medium;

providing, by the BMC, the firmware to the non-volatile memory medium via the multiplexer;

storing, by the non-volatile memory medium, the firmware;

providing, by the BMC, second data to the component via the first bus;

based at least on the second data, providing, by the communications bridge, a second signal to the non-volatile memory medium of the component, the multiplexer of the component, and the integrated circuit, wherein the second signal causes the integrated circuit to be released from the reset state, causes the write protection of the non-volatile memory medium of the component to be instated, and causes the multiplexer of the component to couple the non-volatile memory medium to the integrated circuit; and

executing, by the integrated circuit, the firmware.

9. The method of claim 8 , further comprising:

booting the information handling system;

after the booting the information handling system, providing, by the BMC, third data to the component via the first bus;

based at least on the third data, providing, by the communications bridge, a third signal to the non-volatile memory medium of the component, the multiplexer of the component, and the integrated circuit of the component, wherein the third signal causes the integrated circuit to be held in the reset state, causes the write protection of the non-volatile memory medium of the component to be cleared, and causes the multiplexer of the component to couple the BMC to the non-volatile memory medium;

receiving, by the BMC, the firmware from the non-volatile memory medium;

determining, by the BMC, a first hash value from the firmware;

decrypting, by the BMC, a signature associated with the firmware to obtain a second hash value; and

determining, by the BMC, that the first hash value matches the second hash value.

10. The method of claim 9 , wherein the decrypting, by the BMC, the signature associated with the firmware to obtain the second hash value includes decrypting the signature with a public encryption key.

11. The method of claim 10 , further comprising:

obtaining, by the BMC, the public encryption key from a certificate signed by a certificate authority.

12. The method of claim 8 ,

wherein the communications bridge is coupled to the first bus and is coupled to a second bus;

wherein the multiplexor is coupled to the second bus;

wherein the first bus utilizes a first protocol; and

wherein the second bus utilizes a second protocol, different from the first protocol.

13. The method of claim 12 ,

wherein the first bus includes an inter-integrated circuit bus; and

wherein the second bus includes a serial peripheral interface bus.

14. The method of claim 8 , wherein a Peripheral Component Interconnect Express coupling includes the first bus.

15. A component, configured to be installed in an information handling system, comprising:

a communications bridge configured to be coupled to a first bus of the information handling system;

a non-volatile memory medium;

an integrated circuit; and

a multiplexer, coupled to the communications bridge, the non-volatile memory medium, and the integrated circuit;

wherein the communications bridge is further configured to:

receive first data via the first bus;

based at least on the first data, provide a first signal to the non-volatile memory medium, the multiplexer, and the integrated circuit, wherein the first signal causes the integrated circuit to be held in a reset state, causes a write protection of the non-volatile memory medium to be cleared, and causes the multiplexer to couple the communications bridge to the non-volatile memory medium;

receive, via the first bus, firmware for the integrated circuit;

provide the firmware to the non-volatile memory medium;

receive second data via the first bus; and

based at least on the second data, provide a second signal to the non-volatile memory medium, the multiplexer, and the integrated circuit, wherein the second signal causes the integrated circuit to be released from the reset state, causes the write protection of the non-volatile memory medium to be instated, and causes the multiplexer to couple the non-volatile memory medium to the integrated circuit; and

wherein the integrated circuit is configured to execute the firmware.

16. The component of claim 15 , further comprising:

a second bus;

wherein the second bus couples the communications bridge to the multiplexer.

17. The component of claim 16 ,

wherein the first bus utilizes a first protocol;

wherein the second bus utilizes a second protocol, different from the first protocol.

18. The component of claim 17 ,

wherein the first bus includes an inter-integrated circuit bus; and

wherein the second bus includes a serial peripheral interface bus.

19. The component of claim 15 , wherein the component is a Peripheral Component Interconnect Express component.

20. The component of claim 19 ,

wherein the Peripheral Component Interconnect Express component is coupled to the information handling system via a Peripheral Component Interconnect Express coupling; and

wherein the Peripheral Component Interconnect Express coupling includes the first bus.

Assignments (9)

Continuity (1)