Low dropout regulator and control method thereof
A low dropout regulator is disclosed. The low dropout regulator includes an amplifier, a first transistor, a second transistor and a switch. When a supply voltage value of the low dropout regulator is less than a supply voltage threshold value, a first path of the switch is selected and a first switch voltage value is transmitted to the first transistor so as to fully conduct the first transistor, and an output voltage value of the low dropout regulator is equal to the supply voltage value. When the supply voltage value is not less than the supply voltage threshold value, a second path of the switch is selected and a second switch voltage value is transmitted to the first transistor so as to turn off the first transistor, and the output voltage value is adjusted by the second transistor and the amplifier.
1. A low dropout regulator, comprising:
an amplifier;
a first transistor;
a second transistor, coupled to the amplifier and the first transistor; and
a switch, coupled to the first transistor, wherein when a supply voltage value of the low dropout regulator is less than a supply voltage threshold value, a first path of the switch is selected and a first switch voltage value is transmitted to the first transistor so as to fully conduct the first transistor, and an output voltage value of the low dropout regulator is equal to the supply voltage value, wherein when the supply voltage value is not less than the supply voltage threshold value, a second path of the switch is selected and a second switch voltage value is transmitted to the first transistor so as to turn off the first transistor, and the output voltage value is adjusted by the second transistor and the amplifier, wherein when the output voltage value is less than an output voltage threshold value, an amplifier output value input to the second transistor decreases.
2. The low dropout regulator of claim 1 , wherein the first switch voltage value is 0, and the second switch voltage value is the supply voltage value.
3. The low dropout regulator of claim 1 , wherein the first transistor and the second transistor are PMOS transistors.
4. The low dropout regulator of claim 1 , wherein when the output voltage value is not less than the output voltage threshold value, the amplifier output value input to the second transistor increases.
5. The low dropout regulator of claim 4 , wherein a first input end of the amplifier receives the output voltage threshold value, a second input end of the amplifier receives the output voltage value, and an output end of the amplifier outputs the amplifier output value.
6. The low dropout regulator of claim 4 , wherein when the amplifier output value input to the second transistor decreases, the output voltage value increases, and when the amplifier output value input to the second transistor increases, the output voltage value decreases.
7. A control method of a low dropout regulator, comprising:
transmitting a first switch voltage value to a first transistor so as to fully conduct the first transistor when a supply voltage value is less than a supply voltage threshold value, so that an output voltage value is equal to the supply voltage value;
transmitting a second switch voltage value to the first transistor so as to turn off the first transistor when the supply voltage value is not less than the supply voltage threshold value, so that the output voltage value is adjusted by a second transistor and an amplifier; and
decreasing an amplifier output value input to the second transistor when the output voltage value is less than an output voltage threshold value.
8. The control method of claim 7 , wherein the first switch voltage value is 0 and the second switch voltage value is the supply voltage value.
9. The control method of claim 7 , further comprising:
selecting a first path of a switch so as to transmit the first switch voltage value to the first transistor; and
selecting a second path of the switch so as to transmit the second switch voltage value to the second transistor.
10. The control method of claim 7 , wherein adjusting the output voltage value by the second transistor and the amplifier further comprising:
increasing the amplifier output value input to the second transistor when the output voltage value is not less than the output voltage threshold value.
11. The control method of claim 10 , wherein a conductivity level of the second transistor is in inverse proportional to the amplifier output value.
12. The control method of claim 10 , further comprising:
receiving the output voltage threshold value by a first end of the amplifier;
receiving the output voltage value by a second end of the amplifier; and
outputting the amplifier output value according to the output voltage value and the output voltage threshold value.
13. The control method of claim 12 , further comprising:
increasing the output voltage value when the amplifier output value decreases; and
decreasing the output voltage value when the amplifier output value increases.