Memory arrays comprising vertically-alternating tiers of insulative material and memory cells and methods of forming a memory array
A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor and a capacitor. The capacitor comprises a first electrode electrically coupled to a source/drain region of the transistor. The first electrode comprises an annulus in a straight-line horizontal cross-section and a capacitor insulator radially inward of the first electrode annulus. A second electrode is radially inward of the capacitor insulator. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. A sense line is electrically coupled to another source/drain region of multiple of the transistors that are in different memory-cell tiers. Additional embodiments and aspects are disclosed, including methods.
1. A method of forming a memory array, the memory array comprising memory cells individually comprising a transistor and a capacitor, the method comprising:
forming vertically-alternating tiers of insulative material and transistors, the tiers of transistors comprising horizontally-alternating lines of active area and insulating material, the transistors individually comprising:
a first source/drain region and a second source/drain region having a channel region there-between and a gate operatively proximate the channel region, the gate comprising a portion of a horizontal longitudinally-elongated access line that interconnects multiple of the gates along that access line; individual of the active-area lines comprising the first source/drain region, the second source/drain region, and the channel region;
forming capacitors individually comprising a first electrode and a second electrode having a capacitor insulator there-between, the first electrode being present only within a single of the tiers of transistors and being disposed at an elevation equivalent to the channel region of the transistor, the first electrode being electrically coupled to individual of the first source/drain regions of individual transistors, the second capacitor electrode of multiple of the capacitors in the array being electrically coupled with one another; and
forming a sense-line structure extending elevationally through the vertically-alternating tiers, the second source/drain region of individual transistors that are in different transistor tiers being electrically coupled to the elevationally-extending sense-line structure.
2. The method of claim 1 comprising using masking steps to pattern individual of the transistor tiers before forming the insulative material tier that is immediately-vertically thereover, said masking steps totaling two and only two for each transistor tier.
3. A method of forming a memory array, the memory array comprising memory cells individually comprising a transistor and a capacitor, the method comprising:
forming vertically-alternating tiers of insulative material and transistors, the tiers of transistors comprising horizontally-alternating lines of active area and insulating material, the transistors individually comprising:
a first source/drain region and a second source/drain region having a channel region there-between and a gate operatively proximate the channel region, the gate comprising a portion of a horizontal longitudinally-elongated access line that interconnects multiple of the gates along that access line; individual of the active-area lines comprising the first source/drain region, the second source/drain region, and the channel region;
forming capacitors of individual memory cells, comprising:
forming an opening extending elevationally through multiple of the vertically-alternating tiers;
within the opening, forming a first electrode electrically coupled to the first source/drain region of individual of the transistors, the first electrode being disposed elevationally at an elevation of the channel region of a corresponding individual of the transistors and confined within a single of the tiers of transistors, the first electrode comprising an annulus within the opening;
forming a capacitor insulator within the opening radially inward of the first electrode annulus; and
forming a capacitor-electrode structure within the opening radially inward of the capacitor insulator and extending elevationally through the multiple vertically-alternating tiers, the elevationally-extending capacitor-electrode structure comprising a second electrode of individual of the capacitors; and
forming a sense line electrically coupled to multiple second source/drain regions of the individual transistors that are in different transistor tiers.
4. The method of claim 3 comprising using masking steps to pattern individual of the transistor tiers before forming the insulative material tier that is immediately-vertically thereover, said masking steps totaling two and only two for each transistor tier.
5. The method of claim 3 comprising forming the opening after forming the access line.
6. The method of claim 3 wherein forming the opening comprises widening the opening at least within the transistor tiers before forming the first electrodes.
7. The method of claim 3 wherein forming the first electrode comprises:
within the opening, etching material of the transistor tiers selectively relative to the insulative-material tiers to radially expand the opening and form annular void spaces in the transistor tiers, individual of the annular void spaces extending radially to individual of the first source/drain regions;
forming conductive material in the opening along sidewalls of the opening and in the annular void spaces; and
removing the conductive material from the opening sidewalls and leaving the conductive material in the annular void spaces to form the individual first electrodes.
8. The method of claim 3 comprising forming the capacitor insulator to extend elevationally through the vertically-alternating tiers.
9. The method of claim 3 wherein forming the sense line comprises forming a sense-line structure extending elevationally through the vertically-alternating tiers, individual of the second source/drain regions of the individual transistors being electrically coupled to the elevationally-extending sense-line structure.
10. A method of forming a memory array comprising:
forming vertically-alternating tiers of insulative material and memory cells, the forming the tiers of memory cells comprising forming memory cells individually comprising forming a transistor and forming a capacitor disposed horizontally relative to each other, the forming capacitor comprising:
forming a first electrode electrically coupled to a source/drain region of the transistor, the first electrode being disposed at an elevation over a substrate equivalent to an elevation over the substrate of a channel region of the transistor, the first electrode being disposed within a single of the memory cells and comprising an annulus in a straight-line horizontal cross-section;
forming a capacitor insulator radially inward of the first electrode annulus;
forming a second electrode radially inward of the capacitor insulator; and
forming a capacitor-electrode structure extending elevationally through multiple of the vertically-alternating tiers, individual second electrodes of individual capacitors being electrically coupled to the elevationally-extending capacitor-electrode structure.
11. The method of claim 10 further comprising forming a sense line electrically coupled to another source/drain region of multiple of the transistors that are in different memory-cell tiers.
12. The method of claim 11 wherein the sense line comprises a sense-line structure extending elevationally through the vertically-alternating tiers, individual of the another source/drain regions of individual of the transistors that are in different memory-cell tiers being electrically coupled to the elevationally-extending sense-line structure.
13. The method of claim 12 wherein the sense-line structure comprises a pillar.
14. The method of claim 12 wherein the sense line comprises a horizontal longitudinally-elongated conductive line that is above or below the vertically-alternating tiers and is directly electrically coupled to the sense-line structure.
15. The method of claim 10 wherein the capacitor-electrode structure comprises a pillar.
16. The method of claim 10 wherein the capacitor insulator extends elevationally through the vertically-alternating tiers.
17. The method of claim 10 wherein the capacitor insulator comprises an annulus in a straight-line horizontal cross-section.
18. The method of claim 17 wherein the capacitor insulator extends elevationally through the vertically-alternating tiers.
19. The method of claim 10 wherein the second electrode is not annular in any straight-line horizontal cross-section.
20. The method of claim 10 wherein the capacitor-electrode structure is not annular in any straight-line horizontal cross-section.