IP Library Granted Patent US 11,663,069
Granted Patent B2
US 11,663,069 · App. 17/002,396 · Granted May 30, 2023

Processing system, sensor system, mobile object, abnormality determination method, and non-transitory storage medium

Inventors: Haruko Terai (Osaka, JP); Gentaro Takeda (Osaka, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
G06F11/079G06F11/0724G06F11/0751H04N17/002H04N23/80
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Quick Facts
Patent No.
US 11,663,069
App. No.
17/002,396
Granted
May 30, 2023
Kind
B2
Abstract

A processing system sets up two or more circuits of a plurality of circuits as two or more processing circuits. The two or more processing circuits subject respective input signals from a sensor to signal processing. The processing system sets up at least one circuit of the plurality of circuits to serve as a reference circuit. The at least one circuit being smaller in number than the two or more processing circuits and being other than the processing circuits. The determination circuit is configured to perform abnormality determination for a determination target circuit which is any one of the two or more processing circuits based on a comparison result between an output signal of the determination target circuit and an output signal of the reference circuit.

Claims (53)

1. A processing system, comprising:

a plurality of circuits having a same circuit configuration, each of the plurality of circuits being configured to receive an input signal from a sensor;

a determination circuit; and

a synthesizing circuit, wherein

the processing system is configured to set up two or more circuits of the plurality of circuits to serve as two or more processing circuits, each of the two or more processing circuits being configured to subject the input signal to signal processing,

two or more input signals, each being input to a corresponding one of the two or more processing circuits, include pieces of image data with different exposure times,

the synthesizing circuit is configured to generate a synthesized image by synthesizing output signals output from the two or more processing circuits,

the processing system is configured to set up at least one circuit of the plurality of circuits to serve as a reference circuit, the at least one circuit being smaller in number than the two or more processing circuits and being other than the two or more processing circuits,

a determination target circuit and the reference circuit perform same signal processing on a same input signal, the determination target circuit being one of the two or more processing circuits, and

the determination circuit is configured to, based on a comparison result between an output signal of the determination target circuit and an output signal of the reference circuit, perform abnormality determination to determine whether or not the determination target circuit has an abnormality.

2. The processing system of claim 1 , wherein

the determination target circuit which is subjected to the abnormality determination performed by the determination circuit is changed from one processing circuit of the two or more processing circuits to another processing circuit of the two or more processing circuits over time.

3. The processing system of claim 2 , wherein

a parameter regarding the signal processing on the input signal is set in each of the plurality of circuits, and

the determination target circuit is changed in accordance with a change in the parameter set in the reference circuit.

4. The processing system of claim 2 , further comprising:

an interface circuit configured to receive the input signal from the sensor and output the input signal to each of the plurality of circuits, and

the interface circuit is configured to output, to the reference circuit, an input signal same as the input signal output to the determination target circuit.

5. The processing system of claim 4 , wherein

the interface circuit is configured to change the input signal to be input to the reference circuit at time intervals according to time intervals at which the determination target circuit is changed.

6. The processing system of claim 2 , wherein

the determination target circuit is changed to avoid a plurality of times of the abnormality determination performed for an identical processing circuit of the two or more processing circuits while the determination circuit performs the abnormality determination for all of the two or more processing circuits.

7. The processing system of claim 3 , further comprising:

an interface circuit configured to receive the input signal from the sensor and output the input signal to each of the plurality of circuits, and

the interface circuit is configured to output, to the reference circuit, an input signal a same as the input signal output to the determination target circuit.

8. The processing system of claim 3 , wherein

the determination target circuit is changed to avoid a plurality of times of the abnormality determination performed for an identical processing circuit of the two or more processing circuits while the determination circuit performs the abnormality determination for all of the two or more processing circuits.

9. A processing system comprising:

a plurality of circuits having a same circuit configuration, each of the plurality of circuits being configured to receive an input signal from a sensor; and

a determination circuit, wherein

the processing system is configured to set up two or more circuits of the plurality of circuits to serve as two or more processing circuits, each of the two or more processing circuits being configured to subject the input signal to signal processing,

the processing system is configured to set up at least one circuit of the plurality of circuits to serve as a reference circuit, the at least one circuit being smaller in number than the two or more processing circuits and being other than the two or more processing circuits,

a determination target circuit and the reference circuit perform same signal processing on a same input signal, the determination target circuit being one of the two or more processing circuits,

the determination circuit is configured to, based on a comparison result between an output signal of the determination target circuit and an output signal of the reference circuit, perform abnormality determination to determine whether or not a determination target circuit has an abnormality,

when the determination circuit determines that at least one processing circuit of the two or more processing circuits is abnormal, at least one remaining processing circuit of the two or more processing circuits performs the signal processing on the input signal,

when the determination circuit determines that the reference circuit is abnormal, the reference circuit is changed to any of the plurality of circuits.

10. The processing system of claim 9 , further comprising:

an interface circuit configured to input the input signal from the sensor to each of the plurality of circuits, and

when the determination circuit determines that the at least one processing circuit of the two or more processing circuits is abnormal, the interface circuit outputs the input signal, which is to be output to the at least one processing circuit, to the at least one remaining processing circuit of the two or more processing circuits.

11. A sensor system, comprising:

the processing system of claim 1 ; and

the sensor.

12. A mobile object, comprising:

the sensor system of claim 11 ; and

a mobile object body on which the sensor system is provided.

13. An abnormality determination method, comprising:

setting up two or more circuits of a plurality of circuits having a same circuit configuration, to serve as two or more processing circuits, each of the plurality of circuits being configured to receive an input signal from a sensor, each of the two or more processing circuits being configured to subject the input signal to signal processing;

inputting each of two or more input signals to a corresponding one of the two or more processing circuits, the two or more input signals including pieces of image data with different exposure times,

generating a synthesized image by synthesizing output signals output from the two or more processing circuits;

setting up at least one circuit of the plurality of circuits to serve as a reference circuit, the at least one circuit being smaller in number than the two or more processing circuits and being other than the two or more processing circuits;

performing, by a determination target circuit and the reference circuit, same signal processing on a same input signal, the determination target circuit being one of the two or more processing circuits, and

performing abnormality determination to determine, based on a comparison result between an output signal of the determination target circuit and an output signal of the reference circuit, whether or not the determination target circuit has abnormality.

14. A non-transitory storage medium in which a program is stored, the program being configured to cause a computer system to execute the abnormality determination method of claim 13 .

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2024
From: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
To: PANASONIC AUTOMOTIVE SYSTEMS CO., LTD.
Reel/Frame 066703/0252 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2020
From: TERAI, HARUKO; TAKEDA, GENTARO
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 054643/0561 →
Priority Claims (1)
JP JP2018-179431 · Sep 25, 2018 · national
Continuity (2)
Continuation PCTJP2019037076 · Sep 20, 2019
Related Publication 20200387420A1 · Dec 10, 2020