Frequency-multiplying direct digital synthesizer
A frequency-multiplying DDS includes a digital multiplier, a phase accumulator, a post-accumulator digital processing section, and a digital-to-analog converter (DAC). The digital multiplier multiplies a digital tuning word of value M by a digital multiplier of value B, to produce a digital product (M×B), and the n-bit accumulator accumulates by a step size of the digital product (M×B), at a rate of a low-speed reference clock of frequency f CLK /B. The post-accumulator digital processing section synthesizes B digital waveforms from the sequence of n-bit accumulator output numbers produced by the n-bit accumulator, and rotates each digital waveform with respect to each adjacent digital waveform by (M/2 n )×2π radians. The DAC serializes the digital samples of the B digital waveforms at full speed, i.e., at a rate f CLK , to produce a full-speed serialized digital output having 2 n /M samples per cycle, and converts the full-speed serialized digital output to a final output analog waveform of frequency f OUT =(M/2 n )×f CLK .
1. A direct digital synthesizer (DDS), comprising:
a digital multiplier configured to multiply a digital tuning word by a digital multiplier and produce a digital product;
an accumulator configured to accumulate at a step size of the digital product and at a rate of a reference clock; and
a post-accumulator digital processing section including two or more branches configured to synthesize two or more digital waveforms from a sequence of output numbers produced by the accumulator.
2. The DDS of claim 1 , further comprising:
a serializer configured to serialize digital samples of the two or more digital waveforms and produce an output digital waveform; and
a digital-to-analog converter (DAC) configured to convert the output digital waveform to a final output analog waveform.
3. The DDS of claim 2 , wherein the serializer and DAC together comprise a single interleaved radio frequency DAC (RF-DAC).
4. The DDS of claim 1 , further comprising:
two or more digital-to-analog converters (DACs) configured to convert the two or more digital waveforms to two or more analog waveforms; and
a serializer that samples the two or more analog waveforms to produce a final output analog waveform.
5. The DDS of claim 1 , wherein the two or more branches of the post-accumulator digital processing section comprise:
a zero-offset digital adder in a first branch configured to add, on each cycle of the reference clock, each output number from the sequence of accumulator output numbers to a digital word of value zero; and
one or more step-offset digital adders, each of the one or more step-offset digital adders configured to add, on each cycle of the reference clock, each output number from the sequence of accumulator output numbers to a digital word that is a multiple of the tuning word.
6. The DDS of claim 5 , wherein:
the two or more branches of the post-accumulator digital processing section comprises B branches that synthesize B digital waveforms, where B is a decimal integer equivalent of the digital multiplier and greater than or equal to two;
the one or more step-offset digital adders includes (B−1) branches;
a first digital sum produced by a first step-offset adder in a first one of the (B−1) branches is a first digital number representing a first phase; and
a second digital sum produced by a second step-offset adder in a second one of the (B−1) branches adjacent the first one of the (B−1) branches is a second digital number representing a second phase offset from the first phase by (M/2 n )×2π radians, where M is a number representing the digital tuning word and n is a number representing a word width of the accumulator.
7. The DDS of claim 6 , wherein the B branches of the post-accumulator digital processing section comprises B phase-to-amplitude (φ-to-ρ) converters configured to convert B digital sums produced by the zero-offset and step-offset digital adders to the B digital waveforms.
8. The DDS of claim 1 , wherein the accumulator comprises an n-bit pipelined accumulator, where n is a decimal number representing a word width of the n-bit accumulator.
9. A method of synthesizing a periodic waveform, comprising:
multiplying a digital tuning word by a digital multiplier to produce a digital product;
accumulating at a step size of the digital product and at a rate of a low-speed reference clock to produce a sequence of accumulator output numbers;
generating a first digital waveform from the sequence of accumulator output numbers, at a rate of the low-speed reference clock;
adding the digital tuning word or a multiple of the digital tuning word to each number in the sequence of accumulator output numbers to produce a modified sequence of accumulator output numbers; and
while the first digital waveform is being generated, generating a second digital waveform from the modified sequence of accumulator output numbers, at a rate of the low-speed reference clock.
10. The method of claim 9 , further comprising:
serializing samples of the first and second digital waveforms at a rate of a high-speed reference clock to produce a high-speed serialized digital waveform; and
converting the high-speed serialized digital waveform to a final output analog waveform.
11. The method of claim 10 , wherein the high-speed serialized digital waveform has 2 n /M samples per cycle, and the final output analog waveform has a frequency f OUT =(M/2 n )×f CLK , where M is a value of the digital tuning word and n is a word width of the accumulator.
12. The method of claim 9 , further comprising:
converting the first digital waveform to a first analog waveform;
converting the second digital waveform to a second analog waveform; and
sampling and serializing the first and second analog waveforms, to produce a final output analog waveform.
13. The method of claim 12 , wherein the first and second analog waveforms are sampled and serialized at a rate of a high-speed reference clock, and the final output analog waveform has a frequency f OUT =(M/2 n )×f CLK , where f CLK represents the frequency of the high-speed reference clock, M is a value of the digital tuning word and n is a word width of an accumulator that performs the accumulating.
14. The method of claim 9 , wherein the accumulating is performed by an n-bit pipelined accumulator, where n is a decimal number representing a word width of the n-bit pipelined accumulator.