IP Library Granted Patent US 11,823,968
Granted Patent B2
US 11,823,968 · App. 17/005,003 · Granted Nov 21, 2023

Semiconductor device package having stress isolation and method therefor

Inventors: Michael B. Vincent (Chandler, AZ); Scott M. Hayes (Chandler, AZ); Stephen Ryan Hooper (Mesa, AZ)
Assignee: NXP USA, INC.
H01L23/31H01L21/52H01L21/56H01L23/02
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Quick Facts
Patent No.
US 11,823,968
App. No.
17/005,003
Granted
Nov 21, 2023
Kind
B2
Abstract

A semiconductor device package having stress isolation is provided. The semiconductor device package includes a package substrate and a sensor attached to the package substrate. A first isolation material is formed around a perimeter of the sensor. An encapsulant encapsulates at least a portion of the first isolation material and the package substrate.

Claims (34)

1. A semiconductor device package comprising:

a package substrate;

a sensor die with an active surface and a backside surface opposite to the active surface, the active surface attached to the package substrate;

a first low modulus isolation material formed around a perimeter of the sensor die; and

an encapsulant encapsulating at least a portion of the first low modulus isolation material and the package substrate, wherein the first low modulus isolation material at least laterally isolates the sensor die from the encapsulant, wherein the backside surface of the sensor die is substantially coplanar with a top surface of the encapsulant.

2. The semiconductor device package of claim 1 , further comprising an isolation cavity formed around the perimeter of the sensor die, a bottom of the isolation cavity exposing a portion of the first low modulus isolation material.

3. The semiconductor device package of claim 2 , further comprising a second isolation material disposed in the isolation cavity.

4. The semiconductor device package of claim 1 , further comprising a semiconductor die attached to the package substrate, the encapsulant further encapsulating the semiconductor die.

5. The semiconductor device package of claim 4 , wherein a conductive feed in the package substrate is configured to provide a conductive path between the semiconductor die and the sensor die.

6. The semiconductor device package of claim 1 , wherein the sensor die is characterized as a pressure sensor.

7. The semiconductor device package of claim 1 , wherein the encapsulant encapsulating at least a portion of the first low modulus isolation material and the package substrate is formed by way of a film assisted mold process.

8. The semiconductor device package of claim 1 , further comprising a lid attached over the top surface of the encapsulant and the backside surface of the sensor die.

9. A method of manufacturing a semiconductor device, the method comprising:

placing a sensor die on a carrier substrate, an active surface of the sensor die contacting the carrier substrate;

dispensing a first low modulus isolation material around a perimeter of the sensor die;

encapsulating with an encapsulant at least a portion of the first low modulus isolation material and the carrier substrate, the first low modulus isolation material at least laterally isolating the sensor die from the encapsulant;

exposing a backside surface of the sensor die such that it is substantially coplanar with a top surface of the encapsulant, the backside surface of the sensor die opposite of the active surface of the sensor die; and

after removing the carrier substrate, applying a package substrate on the active surface of the sensor die and bottom surfaces of the first low modulus isolation material and the encapsulant.

10. The method of claim 9 , further comprising forming an isolation cavity around the perimeter of the sensor die, a bottom of the isolation cavity exposing a portion of the first low modulus isolation material.

11. The method of claim 10 , wherein exposing the backside surface of the sensor die such that it is substantially coplanar with the top surface of the encapsulant comprises back-grinding the top surface of the encapsulant to expose the backside surface of the sensor die before forming the isolation cavity.

12. The method of claim 10 , further comprising dispensing a second isolation material into the isolation cavity around the perimeter of the sensor die.

13. The method of claim 10 , further comprising attaching a lid over the top surface of the encapsulant and the backside surface of the sensor die.

14. The method of claim 9 , further comprising placing a semiconductor die on the carrier substrate before encapsulating with the encapsulant, and wherein a conductive feed in the package substrate is configured to provide a conductive path between the semiconductor die and the sensor die.

15. The method of claim 9 , wherein encapsulating with an encapsulant further comprises encapsulating by way of a film assisted molding process such that a top surface of the first low modulus isolation material is exposed.

16. A semiconductor device package comprising:

a package substrate;

a sensor die with an active surface and a backside surface, the active surface attached to the package substrate;

a first low modulus isolation material formed around a perimeter of the sensor die;

an encapsulant to encapsulate at least a portion of the sensor die and the package substrate, the first low modulus isolation material to at least laterally isolate the sensor die from the encapsulant, wherein the backside surface of the sensor die is substantially coplanar with a top surface of the encapsulant; and

an isolation cavity formed around the perimeter of the sensor die, a bottom of the isolation cavity exposing a portion of the first low modulus isolation material.

17. The semiconductor device package of claim 16 , further comprising a second isolation material disposed in the isolation cavity.

18. The semiconductor device package of claim 16 , further comprising a semiconductor die attached to the package substrate, the encapsulant further encapsulating the semiconductor die.

19. The semiconductor device package of claim 18 , wherein a conductive feed in the package substrate is configured to provide a conductive path between the semiconductor die and the sensor die.

20. The semiconductor device package of claim 16 , further comprising a lid attached over the top surface of the encapsulant and the backside surface of the sensor die.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2026
From: NXP USA, INC.
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 075127/0364 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2020
From: VINCENT, MICHAEL B.; HAYES, SCOTT M.; HOOPER, STEPHEN RYAN
To: NXP USA, INC.
Reel/Frame 053620/0245 →
Continuity (1)
Related Publication 20220068738A1 · Mar 3, 2022