Memory system and operating method thereof
A memory system includes a memory device including a plane including a plurality of memory blocks for storing multi-bit data; and a controller configured to detect, when a problem-causing operation is performed on a first memory block among the memory blocks, remaining memory blocks, except the first memory block, in the plane as being in a problem occurrence candidate group, search for a table, when a read command for a second memory block of the problem occurrence candidate group is received, for a read voltage application order corresponding to the second memory block, and control the memory device to perform a read operation on the second memory block by sequentially applying a plurality of read voltages according to the searched read voltage application order, wherein the problem-causing operation is a program operation or an erase operation.
1. A memory system comprising:
a memory device including a plane including a plurality of memory blocks for storing multi-bit data; and
a controller configured to:
detect, when a problem-causing operation is performed on a first memory block among the memory blocks, remaining memory blocks, except the first memory block, in the plane as being in a problem occurrence candidate group,
search a table, when a read command for a second memory block of the problem occurrence candidate group is received, for a read voltage application order corresponding to the second memory block, and
control the memory device to perform a read operation on the second memory block by sequentially applying a plurality of read voltages according to the searched read voltage application order,
wherein the problem-causing operation is a program operation or an erase operation,
wherein the controller controls, in response to the read command immediately after the problem-causing operation, the memory device to perform a first read operation on the second memory block based on a secondary set of the plurality of read voltages; and
controls, in response to the read command immediately after a successful read operation set including the first read operation on the second memory block, the memory device to perform a second read operation on the second memory block based on a primary set of the plurality of read voltages.
2. The memory system according to claim 1 , wherein the table includes read voltage application orders corresponding to the plurality of memory blocks, respectively.
3. The memory system according to claim 1 , wherein the controller is further configured to exclude the second memory block from the problem occurrence candidate group after performing the read operation.
4. The memory system according to claim 1 , wherein the controller is further configured to set a flag bit for each memory block within the problem occurrence candidate group to a logic high level.
5. The memory system according to claim 3 , wherein the controller excludes the second memory block from the problem occurrence candidate group by setting a flag bit for the second memory block to a logic low level.
6. The memory system according to claim 1 , wherein the controller is further configured to control the memory device to perform a read retry operation when the read operation fails.
7. The memory system according to claim 1 , wherein the table includes a plurality of read voltage application orders.
8. The memory system according to claim 7 , wherein the read operation on the second memory block based on the read voltage application order determined by shifts of threshold voltage distributions due to the problem-causing operation.
9. The memory system according to claim 5 , wherein the controller is further configured to control the memory device to perform a read operation according to a default read voltage application order, when a flag bit for a memory block corresponding to a subsequent read command is a logic low level.
10. The memory system according to claim 1 , wherein the controller is further configured to output error-corrected data when the read operation succeeds.
11. A method for operating a memory system, comprising:
performing a problem-causing operation on a first memory block among memory blocks included in a plane, in which multi-bit data is stored in each cell;
detecting remaining memory blocks, except the first memory block, in the plane, as being in a problem occurrence candidate group;
receiving a read command for a second memory block of the problem occurrence candidate group;
searching for a read voltage application order corresponding to the second memory block from a table; and
performing a read operation on the second memory block by sequentially applying a plurality of read voltages according to the searched read voltage application order,
wherein the problem-causing operation is a program operation or an erase operation,
wherein the performing of the read operation includes:
performing, in response to the read command immediately after the problem-causing operation, a first read operation on the second memory block based on a secondary set of the plurality of read voltages; and
performing, in response to the read command immediately after a successful read operation set including the first read operation on the second memory block, a second read operation on the second memory block based on a primary set of the plurality of read voltages.
12. The method according to claim 11 , wherein the table includes read voltage application orders corresponding to the memory blocks, respectively.
13. The method according to claim 11 , further comprising: excluding the second memory block from the problem occurrence candidate group after the read operation is performed.
14. The method according to claim 11 , further comprising setting a flag bit for each memory block within the problem occurrence candidate group to a logic high level.
15. The method according to claim 13 , wherein the excluding includes setting a flag bit for the second memory block to a logic low level.
16. The method according to claim 11 , further comprising: performing a read retry operation when the read operation fails.
17. The method according to claim 11 , wherein the table includes a plurality of read voltage application orders.
18. The method according to claim 17 , wherein the read operation on the second memory block based on the searched read voltage application order determined by shifts of threshold voltage distributions due to the problem-causing operation.
19. The method according to claim 15 , further comprising: performing a read operation according to a default read voltage application order, when a flag bit for a memory block corresponding to a subsequent read command is a logic low level.
20. An operating method of a controller, the operating method comprising:
controlling a memory device to perform a program operation or an erase operation on a first block;
controlling, in response to a command immediately after the program or erase operation, the memory device to perform a first default read operation on a second block based on a secondary set of read voltages, the second block neighboring the first block; and
controlling, in response to a command immediately after a successful read operation set including the first default read operation on the second block, the memory device to perform a second default read operation on the second block based on a primary set of read voltages,
wherein the primary and secondary sets have different application orders of the read voltages.