System and method for baseboard management controller boot first resiliency
An information handling system includes a processor, a BMC, and a logic device. The BMC boots in response to an AC power cycle event, provides a BMC ready signal in response to the boot, establishes the BMC as a root of trust for the processor in response to providing the BMC ready signal, and provides a processor boot indication to the processor in response to establishing the BMC as the root of trust. The processor boots to an operating system in response to the processor boot indication instead of in response to the AC power cycle. The logic device determines that the BMC failed to provide the BMC ready signal, determines that the BMC failed to boot in response to the AC power cycle and determining that the BMC failed to provide the BMC ready signal, and provides a power-on reset signal to the BMC in response to determining that the BMC failed to boot.
1. An information handling system, comprising:
a processor;
a baseboard management controller (BMC) configured, in response to an AC power cycle event, to:
boot;
provide a BMC ready signal in response to the boot;
establish the BMC as a root of trust for the processor in response to providing the BMC ready signal; and
provide a first processor boot indication to the processor in response to establishing the BMC as the root of trust, wherein the processor is configured to boot to an operating system in response to the first processor boot indication instead of in response to the AC power cycle; and
a logic device configured to:
determine that the BMC failed to provide the BMC ready signal;
determine that the BMC failed to boot a first time in response to the AC power cycle, and further in response to determining that the BMC failed to provide the BMC ready signal; and
provide a power-on reset signal to the BMC in response to determining that the BMC failed to boot the first time.
2. The information handling system of claim 1 , wherein the logic device is further configured to:
set a watch dog timer prior to determining that the BMC failed to provide the BMC ready signal; and
determine that the watch dog timer has timed out in response to determining that the BMC failed to boot the first time, wherein providing the power-on reset signal is in further response to determining that the watch dog timer has timed out.
3. The information handling system of claim 2 , wherein in determining that the BMC failed to boot the first time, the logic device is further configured to:
increment a BMC boot failure counter; and
determine that a value of the BMC boot failure counter is equal to 1.
4. The information handling system of claim 3 , wherein the logic device is further configured to:
determine that the BMC failed to boot a second time in response to the AC power cycle, and further in response to determining that the BMC failed to provide the BMC ready signal; and
initiate a virtual AC power cycle event on the information handling system in response to determining that the BMC failed to boot the second time.
5. The information handling system of claim 4 , wherein the logic device is further configured to:
determine that the watch dog timer has timed out in response to determining that the BMC failed to boot the second time, wherein initiating the virtual AC power cycle event is in further response to determining that the watch dog timer has timed out.
6. The information handling system of claim 5 , wherein in determining that the BMC failed to boot the second time, the logic device is further configured to:
increment the BMC boot failure counter; and
determine that a value of the BMC boot failure counter is equal to 2.
7. The information handling system of claim 6 , wherein:
the logic device is further configured to:
determine that the BMC failed to boot a third time in response to the AC power cycle, and further in response to determining that the BMC failed to provide the BMC ready signal; and
provide a second processor boot indication to the processor in response determining that the BMC failed to boot the third time; and
wherein the processor is further configured to boot in a safe mode boot in response to the second processor boot indication, wherein the safe mode does not include booting to an operating system.
8. The information handling system of claim 7 , wherein in determining that the BMC failed to boot the third time, the logic device is further configured to:
increment the BMC boot failure counter; and
determine that a value of the BMC boot failure counter is equal to 3.
9. The information handling system of claim 1 , wherein, in response to booting the processor to the operating system, the logic device is further configured to:
determine that the BMC failed to provide the BMC ready signal; and
provide a core reset signal to the BMC in response to determining that the BMC failed to boot the first time, the core reset to reset a processor device of the BMC.
10. The information handling system of claim 9 , wherein the logic device is further configured to:
set a watch dog timer prior to determining that the BMC failed to provide the BMC ready signal; and
determine that the watch dog timer has timed out in response prior to providing the core reset signal.
11. A method, comprising:
booting a baseboard management controller (BMC) of an information handling system;
providing, by the BMC, a ready signal in response to booting the BMC,
establishing, by the BMC, the BMC as a root of trust for a processor of the information handling system in response to providing the BMC ready signal;
providing a first processor boot indication to the processor in response to establishing the BMC as the root of trust;
booting the processor to boot to an operating system in response to the first processor boot indication instead of in response to the AC power cycle;
determining, by a logic device of the information handling system, that the BMC failed to provide the BMC ready signal;
determining, by the logic device, that the BMC failed to boot a first time in response to the AC power cycle, and further in response to determining that the BMC failed to provide the BMC ready signal; and
providing a power-on reset signal to the BMC in response to determining that the BMC failed to boot the first time.
12. The method of claim 11 , further comprising:
setting a watch dog timer prior to determining that the BMC failed to provide the BMC ready signal; and
determining that the watch dog timer has timed out in response to determining that the BMC failed to boot the first time, wherein providing the power-on reset signal is in further response to determining that the watch dog timer has timed out.
13. The methods of claim 12 , wherein in determining that the BMC failed to boot the first time, the method further comprises:
incrementing a BMC boot failure counter; and
determining that a value of the BMC boot failure counter is equal to 1.
14. The method of claim 13 , further comprising:
determining that the BMC failed to boot a second time in response to the AC power cycle, and further in response to determining that the BMC failed to provide the BMC ready signal; and
initiating a virtual AC power cycle event on the information handling system in response to determining that the BMC failed to boot the second time.
15. The method of claim 14 , further comprising:
determining that the watch dog timer has timed out in response to determining that the BMC failed to boot the second time, wherein initiating the virtual AC power cycle event is in further response to determining that the watch dog timer has timed out.
16. The method of claim 15 , wherein in determining that the BMC failed to boot the second time, the method further comprises:
incrementing the BMC boot failure counter; and
determining that a value of the BMC boot failure counter is equal to 2.
17. The method of claim 16 , further comprising:
determining that the BMC failed to boot a third time in response to the AC power cycle, and further in response to determining that the BMC failed to provide the BMC ready signal;
providing a second processor boot indication to the processor in response determining that the BMC failed to boot the third time; and
booting the processor in a safe mode boot in response to the second processor boot indication, wherein the safe mode does not include booting to an operating system.
18. The method of claim 17 , wherein in determining that the BMC failed to boot the third time, the method further comprises:
incrementing the BMC boot failure counter; and
determining that a value of the BMC boot failure counter is equal to 3.
19. The method of claim 11 , wherein, in response to booting the processor to the operating system, the method further comprises:
determining that the BMC failed to provide the BMC ready signal; and
providing a core reset signal to the BMC in response to determining that the BMC failed to boot the first time, the core reset to reset a processor device of the BMC.
20. An information handling system, comprising:
a power supply;
a baseboard management controller (BMC) configured, in response to an AC power cycle event from the power supply, to:
boot;
provide a BMC ready signal in response to the boot;
establish the BMC as a root of trust for a processor in response to providing the BMC ready signal; and
provide a first processor boot indication to the processor in response to establishing the BMC as the root of trust, wherein the processor is configured to boot to an operating system in response to the first processor boot indication instead of in response to the AC power cycle; and
a logic device configured to:
determine that the BMC failed to provide the BMC ready signal;
determine that the BMC failed to boot a first time in response to the AC power cycle, and further in response to determining that the BMC failed to provide the BMC ready signal; and
provide a power-on reset signal to the BMC in response to determining that the BMC failed to boot the first time.