Split gate charge trapping memory cells having different select gate and memory gate heights
A semiconductor device and method of making such device is presented herein. The method includes disposing a gate layer over a dielectric layer on a substrate and further disposing a cap layer over the gate layer. A first transistor gate is defined having an initial thickness substantially equal to a combined thickness of the cap layer and the gate layer. A first doped region is formed in the substrate adjacent to the first transistor gate. The cap layer is subsequently removed and a second transistor gate is defined having a thickness substantially equal to the thickness of the gate layer. Afterwards, a second doped region is formed in the substrate adjacent to the second transistor gate. The first doped region extends deeper in the substrate than the second doped region, and a final thickness of the first transistor gate is substantially equal to the thickness of the second transistor gate.
1. A method of fabricating a split gate memory device, comprising:
forming a first dielectric layer and a memory gate layer over at least a first region of a substrate; forming a cap layer over the memory gate layer; patterning the cap, memory gate, and first dielectric layers to form a memory gate stack forming a second dielectric layer over the memory gate stack; forming a select gate layer overlying the second dielectric layer; patterning the select gate layer such that only a single select gate stack is formed adjacent to the memory gate stack; forming doped regions within the substrate adjacent to the memory gate stack and the select gate stack, respectively; and removing the cap layer from the memory gate stack, wherein forming the select gate stack comprises forming the select gate stack to comprise a planar top surface parallel to a surface of the substrate.
2. The method of claim 1 , wherein forming the first dielectric layer includes disposing a charge trapping layer overlying the substrate.
3. The method of claim 1 , wherein patterning the cap, memory gate, and first dielectric layers includes performing an etching process to remove the cap, memory gate, and first dielectric layers beyond the memory gate stack.
4. The method of claim 3 , wherein the etching process includes at least one of reactive ion etching, hot acid baths, a dry etching process, or a wet etching process.
5. The method of claim 1 , wherein forming the second dielectric layer includes disposing the second dielectric layer conformably over two side surfaces and a top surface of the memory gate stack.
6. The method of claim 1 , wherein patterning the select gate layer includes: performing an etch-back process on the select gate layer across the substrate such that the select gate layer is removed in all areas except in areas adjacent to the memory gate stack.
7. The method of claim 5 , wherein the select gate layer patterned is self-aligned adjacent to the side surfaces of the memory gate stack, and further comprising:
removing the select gate layer patterned adjacent to one of the side surfaces of the memory gate stack.
8. The method of claim 1 , wherein forming the doped regions includes forming a drain region adjacent to the select gate stack and a drain region adjacent to the memory gate stack.
9. The method of claim 1 , wherein a top surface of the select gate stack has a higher elevation than the top surface of the memory gate stack after the cap layer is removed.
10. The method of claim 1 , wherein the cap layer is selectively removable and configured to control a height of the memory gate layer in the memory gate stack.
11. The method of claim 1 , wherein a vertical portion of the second dielectric layer is disposed between the memory and select gate stacks.
12. The method of claim 1 , further comprising:
forming a low-voltage transistor including a first gate layer disposed over a low-voltage dielectric layer in a second region of the substrate; and
forming a high-voltage transistor including the first gate layer disposed over a high-voltage dielectric layer in a third region of the substrate, wherein the high-voltage dielectric layer is thicker than the low-voltage dielectric layer.
13. The method of claim 1 , wherein forming the memory gate stack comprises forming the memory gate stack to comprise a planar top surface parallel to a surface of the substrate.