Non-volatile memory device

1. A non-volatile memory, comprising:

an upper semiconductor layer including a first metal pad and vertically stacked on a lower semiconductor layer, wherein the upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region,

the lower semiconductor layer includes a second metal pad and a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group, and

the upper semiconductor layer is vertically connected to the lower semiconductor layer by the first metal pad and the second metal pad.

2. The non-volatile memory of claim 1 , further comprising:

a control logic that generates a connection control signal, wherein the bypass circuit selectively connects the first bit line with the second bit line in response to the connection control signal.

3. The non-volatile memory of claim 1 , wherein the bypass circuit includes a transistor including a first source/drain region and a second source/drain region, and

the non-volatile memory device further comprises:

a first contact plug extending from the first source/drain region through the separation region to connect the first bit line; and

a second contact plug extending from the second source/drain region through the separation region to connect the second bit line.

4. The non-volatile memory of claim 3 , wherein the transistor further includes a gate, and

the non-volatile memory device further comprises:

a control logic that generates a connection control signal applied to the gate, wherein the bypass circuit selectively connects the first bit line with the second bit line in response to the connection control signal.

5. The non-volatile memory of claim 1 , wherein a portion of the lower semiconductor layer underlying the first memory group includes a first portion of a first row decoder, a second portion of the first row decoder, a first portion of a first page buffer and a second portion of the first page buffer arranged in a first windmill pattern, and

another portion of the lower semiconductor layer underlying the second memory group includes a first portion of a second row decoder, a second portion of the second row decoder, a first portion of a second page buffer and a second portion of the second page buffer arranged in a second windmill pattern.

6. The non-volatile memory of claim 1 , further comprising:

a lower substrate underlying the lower semiconductor layer;

a first upper substrate and a second upper substrate,

wherein the separation region extends between the first upper substrate and the second upper substrate.

7. The non-volatile memory of claim 6 , further comprising:

a first vertical structure disposed below the first upper substrate and including memory cells of the first memory group and a second vertical structure disposed below the second upper substrate and including memory cells of the second memory group,

wherein the first bit lines including the first bit line are disposed below the first vertical structure and extend in the first horizontal direction,

the second bit lines including the second bit line are disposed below the second vertical structure and extend in the first horizontal direction, and

the first bit lines and second bit lines are electrically insulated from one another by the separation region.

8. The non-volatile memory of claim 1 , wherein the lower semiconductor layer further includes a control logic that generates a connection control signal, and the bypass circuit selectively connects the first bit line and the second bit line in response to the connection control signal.

9. The non-volatile memory of claim 1 , wherein the lower semiconductor layer further includes a pad region disposed along at least a portion of at least one outer edge of the lower semiconductor layer.

10. The non-volatile memory of claim 1 , wherein the bypass circuit includes a transistor having a first source/drain region and a second source/drain region, and

the non-volatile memory device further comprises:

a lower substrate underlying the lower semiconductor layer;

a first upper substrate and a second upper substrate, wherein the separation region extends between the first upper substrate and the second upper substrate;

a first vertical structure disposed below the first upper substrate and including memory cells of the first memory group;

a second vertical structure disposed below the second upper substrate and including memory cells of the second memory group;

a first contact plug extending vertically from the first vertical structure to connect the first bit line;

a second contact plug extending vertically from the second vertical structure to connect the second bit line;

a third contact plug connecting the first source/drain region;

a fourth contact plug connecting the second source/drain region;

a first conductive line extending in the first horizontal direction and connecting the first contact plug and the third contact plug; and

a second conductive line extending in the first horizontal direction and connecting the second contact plug and the fourth contact plug.

11. The non-volatile memory of claim 1 , wherein the bypass circuit includes a transistor having a first source/drain region and a second source/drain region, and

the non-volatile memory device further comprises:

a lower substrate underlying the lower semiconductor layer;

a first upper substrate and a second upper substrate;

a first vertical structure disposed below the first upper substrate and including a first edge region and memory cells of the first memory group;

a second vertical structure disposed below the second upper substrate and including a second edge region and memory cells of the second memory group, wherein the separation region extends between the first edge region and the second edge region;

a first contact plug extending vertically from the first vertical structure to connect the first bit line;

a second contact plug extending vertically from the second vertical structure to connect the second bit line;

a third contact plug connecting the first source/drain region;

a fourth contact plug connecting the second source/drain region;

a first conductive line extending in the first horizontal direction and connecting the first contact plug and the third contact plug; and

a second conductive line extending in the first horizontal direction and connecting the second contact plug and the fourth contact plug,

wherein the bypass circuit is disposed in a portion of the first semiconductor layer underlying one of the first edge region and the second edge region.

12. A three-dimensional (3D), non-volatile memory, comprising:

a control logic that generates a connection control signal;

an upper semiconductor layer including a first metal pad and vertically stacked on a lower semiconductor layer,

wherein the upper semiconductor layer includes a first memory group electrically isolated from a second memory group by a separation region, the first memory group including a first set of tiles including a first tile incorporating a first memory cell array, and the second memory group including a second set of tiles including a second tile incorporating a second memory cell array, and

the lower semiconductor layer includes a second metal pad and a bypass circuit underlying at least a portion of the separation region, wherein the bypass circuit is configured to selectively connect a first bit line of the first tile with a second bit line of the second tile in response to the connection control signal, and

the upper semiconductor layer is vertically connected to the lower semiconductor layer by the first metal pad and the second metal pad.

13. The 3D non-volatile memory of claim 12 , wherein the bypass circuit includes a transistor including a gate receiving the connection control signal, a first source/drain region and a second source/drain region, and

the 3D non-volatile memory device further comprises:

a first contact plug extending from the first source/drain region through the separation region to connect the first bit line; and

a second contact plug extending from the second source/drain region through the separation region to connect the second bit line.

14. The 3D non-volatile memory of claim 12 , wherein a portion of the lower semiconductor layer underlying the first memory group includes a first portion of a first row decoder, a second portion of the first row decoder, a first portion of a first page buffer and a second portion of the first page buffer arranged in a first windmill pattern, and

another portion of the lower semiconductor layer underlying the second memory group includes a first portion of a second row decoder, a second portion of the second row decoder, a first portion of a second page buffer and a second portion of the second page buffer arranged in a second windmill pattern.

15. The 3D non-volatile memory of claim 12 , further comprising:

a lower substrate underlying the lower semiconductor layer;

a first upper substrate and a second upper substrate,

wherein the separation region extends between the first upper substrate and the second upper substrate.

16. The 3D non-volatile memory of claim 15 , further comprising:

a first vertical structure disposed below the first upper substrate and including memory cells of the first tile and a second vertical structure disposed on the second upper substrate and including memory cells of the second tile,

wherein the first bit lines including the first bit line are disposed below the first vertical structure and second bit lines including the second bit line are disposed below the second vertical structure.

17. The 3D non-volatile memory of claim 12 , wherein the control logic is disposed in the lower semiconductor layer, and the 3D non-volatile memory further comprises a pad region disposed along at least a portion of at least one outer edge of the lower semiconductor layer.

18. The 3D non-volatile memory of claim 12 , wherein the bypass circuit includes a transistor having a first source/drain region and a second source/drain region, and

the non-volatile memory device further comprises:

a lower substrate underlying the lower semiconductor layer;

a first upper substrate and a second upper substrate, wherein the separation region extends between the first upper substrate and the second upper substrate;

a first vertical structure disposed below the first upper substrate and including memory cells of the first tile;

a second vertical structure disposed below the second upper substrate and including memory cells of the second tile;

a first contact plug extending vertically from the first vertical structure to connect the first bit line;

a second contact plug extending vertically from the second vertical structure to connect the second bit line;

a third contact plug connecting the first source/drain region;

a fourth contact plug connecting the second source/drain region;

a first conductive line extending in the first horizontal direction and connecting the first contact plug and the third contact plug; and

a second conductive line extending in the first horizontal direction and connecting the second contact plug and the fourth contact plug.

19. The 3D non-volatile memory of claim 12 , wherein the bypass circuit includes a transistor having a first source/drain region and a second source/drain region, and

the non-volatile memory device further comprises:

a lower substrate underlying the lower semiconductor layer;

a first upper substrate and a second upper substrate;

a first vertical structure disposed below the first upper substrate and including a first edge region and memory cells of the first tile;

a second vertical structure disposed below the second upper substrate and including a second edge region and memory cells of the second tile, wherein the separation region extends between the first edge region and the second edge region;

a first contact plug extending vertically from the first vertical structure to connect the first bit line;

a second contact plug extending vertically from the second vertical structure to connect the second bit line;

a third contact plug connecting the first source/drain region;

a fourth contact plug connecting the second source/drain region;

a first conductive line extending in the first horizontal direction and connecting the first contact plug and the third contact plug; and

a second conductive line extending in the first horizontal direction and connecting the second contact plug and the fourth contact plug,

wherein the bypass circuit is disposed in a portion of the first semiconductor layer underlying one of the first edge region and the second edge region.

20. The 3D non-volatile memory of claim 12 , wherein the first set of tiles is physically separated from the second set of tiles by the separation region.