Cryptographic data integrity protection
A storage device includes a memory storage region and a controller having a processor. The processor retrieves user data from the memory storage region using a physical block address corresponding to a logical block address (LBA), in response to a read command. The retrieved user data includes a first hash received through a host interface in a prior host data transmission. The processor further performs error correction on the user data to generate error-corrected user data. The processor further causes a cryptographic engine to produce a second hash of the error-corrected user data. The first hash is compared to the second hash associated with the error-corrected user data to determine a match result. A notification is generated in response to the match result.
1. A storage device that implements cryptographic validity checking, the storage device comprising:
a memory storage region; and
a controller having a processor configured to execute instructions stored on the storage device, wherein the instructions, when executed by the processor, cause the processor to perform operations comprising:
retrieving user data from the memory storage region using a physical block address corresponding to a logical block address (LBA), in response to a read command, the retrieved user data having a first hash received through a host interface in a prior host data transmission;
performing error correction on the user data to generate error-corrected user data;
causing a cryptographic engine to produce a second hash of the error-corrected user data, the second hash produced based on a cryptographic key shared with the host;
comparing the first hash to the second hash associated with the error-corrected user data to determine a match result; and
generating a notification in response to the match result.
2. The storage device of claim 1 , wherein the operations comprise:
detecting whether the memory storage region is an integrity-protected memory region based on the LBA; and
causing, on detecting that the memory storage region is an integrity-protected memory region, the cryptographic engine to produce the second hash of the error-corrected user data.
3. The storage device of claim 1 , wherein the prior host data transmission includes a write command, and wherein the first hash was stored in the memory storage region during performance of the write command.
4. The storage device of claim 3 , wherein the first hash is stored in a spare area of the memory storage region, wherein the spare area is read atomically with a user area storing the user data.
5. The storage device of claim 3 , wherein the user data is stored in a user area of the memory storage region, and the first hash is stored in the user area using a pre-defined offset from the user data.
6. The storage device of claim 5 , wherein the first hash is stored in a user data portion of the user area which is inaccessible to the host.
7. The storage device of claim 1 , wherein the operations comprise:
generating a failure notification as a status of the read command when the first hash does not match the second hash.
8. The storage device of claim 1 , wherein the operations comprise:
storing the error-corrected user data in a buffer for communication to the host when the first hash matches the second hash.
9. The storage device of claim 1 , wherein the first hash is obtained using metadata of the prior host data transmission.
10. The storage device of claim 1 , wherein the first hash is generated by the host using the cryptographic key.
11. The storage device of claim 1 , wherein the prior host data transmission includes a first communication for the user data and a second communication for the first hash.
12. The storage device of claim 1 , wherein the first hash and the second hash are keyed-hash message authentication codes (HMACs).
13. The storage device of claim 1 , wherein the host interface of the storage device conforms to at least one of an Integrated Device Electronics (IDE) AT Attachment (ATA) interface, a serial ATA (SATA) interface, a Small Computer System Interface (SCSI) interface, a Universal Flash Storage (UFS) interface, an embedded MultiMedia Card (eMMC) interface, or Non-Volatile Memory Host Controller Interface Specification (NVMHCI) interface.
14. The storage device of claim 1 , wherein the memory storage region comprises one or more flash memory die.
15. A method, comprising:
retrieving user data from a memory storage region using a physical block address (PBA) corresponding to a logical block address (LBA), in response to a read command, the retrieved user data having a first hash received through a host interface in a prior host data transmission;
performing error correction on the user data to generate error-corrected user data;
causing a cryptographic engine to produce a second hash of the error-corrected user data, the second hash produced based on a cryptographic key shared with the host;
comparing the first hash to the second hash associated with the error-corrected user data to determine a match result; and
generating a notification in response to the match result.
16. The method of claim 15 , further comprising:
detecting whether the memory storage region is an integrity-protected memory region, based on the LBA; and
causing, on detecting that the memory storage region is an integrity-protected memory region, the cryptographic engine to produce the second hash of the error-corrected user data.
17. The method of claim 15 , further comprising:
generating a failure notification as a status of the read command when the first hash does not match the second hash.
18. The method of claim 15 , further comprising:
storing the error-corrected user data in a buffer for communication to the host when the first hash matches the second hash.
19. A machine-readable medium, comprising instructions, which when executed by a processor of a storage device, cause the processor to perform operations comprising:
retrieving user data from a memory storage region using a physical block address (PBA) corresponding to a logical block address (LBA), in response to a read command, the retrieved user data having a first hash received through a host interface in a prior host data transmission;
performing error correction on the user data to generate error-corrected user data;
causing a cryptographic engine to produce a second hash of the error-corrected user data, the second hash produced based on a cryptographic key shared with the host;
comparing the first hash to the second hash associated with the error-corrected user data to determine a match result; and
generating a notification in response to the match result.
20. The machine-readable medium of claim 19 , the operations further comprising:
detecting whether the memory storage region is an integrity-protected memory region, based on the LBA; and
causing, on detecting that the memory storage region is an integrity-protected memory region, the cryptographic engine to produce the second hash of the error-corrected user data.
21. The machine-readable medium of claim 19 , the operations further comprising:
generating a failure notification as a status of the read command when the first hash does not match the second hash.
22. The machine-readable medium of claim 19 , the operations further comprising:
storing the error-corrected user data in a buffer for communication to the host when the first hash matches the second hash.