IP Library › Granted Patent US 11,658,479
Granted Patent B2
US 11,658,479 · App. 17/015,695 · Granted May 23, 2023

Low leakage MOSFET supply clamp for electrostatic discharge (ESD) protection

Inventors: Radhakrishnan Sithanandam (Greater Noida, IN); Divya Agarwal (Noida, IN); Ghislain Troussier (Voiron, FR); Jean Jimenez (Saint Theoffrey, FR); Malathi Kar (Delhi, IN)
Assignees: STMicroelectronics International N.V.; STMicroelectronics SA
H02H9/046H01L27/0255H01L27/0266H01L27/0288H01L27/0285
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Quick Facts
Patent No.
US 11,658,479
App. No.
17/015,695
Granted
May 23, 2023
Kind
B2
Abstract

Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated MOSFET device. Triggering of the MOSFET device is made at both the gate terminal and the substrate (back gate) terminal. Additionally, the MOSFET device can be formed of cascoded MOSFETs.

Claims (70)

1. An electrostatic discharge (ESD) protection circuit, comprising:

a first power supply line;

a second power supply line;

a first MOSFET device of a first conductivity type;

a second MOSFET device of said first conductivity type;

wherein source-drain paths of the first and second MOSFET devices are connected in series between the first power supply line and the second power supply line; and

a trigger circuit configured to generate, in response to detection of an ESD event at one or more of the first and second power supply lines, one or more trigger signals for application to gate terminals of the first and second MOSFET devices.

2. The circuit of claim 1 , further comprising a functional circuit electrically coupled for power supply to the first and second power supply lines.

3. The circuit of claim 1 , wherein the trigger circuit comprises:

a resistive-capacitive ESD detection circuit configured to generate an ESD detection signal;

a first inverter circuit having an input coupled to receive the ESD detection signal; and

a second inverter circuit having an input coupled to an output of the first inverter circuit and an output configured to generate a first trigger signal of said one or more trigger signals which is applied to the gate terminals of both the first and second MOSFET devices.

4. The circuit of claim 3 , further comprising a third MOSFET device of a second first conductivity type opposite the first conductivity type having a first conduction terminal connected to the gate terminals of both the first and second MOSFET devices, a second conduction terminal connected to the second power supply line, and a gate terminal connected to the first power supply line.

5. The circuit of claim 1 , wherein the trigger circuit is configured to generate, in response to detection of an ESD event at one or more of the first and second power supply lines, a first trigger signal for application to gate terminal of the first MOSFET device and a second trigger signal, different from said first trigger signal, for application to the gate terminal of the second MOSFET device.

6. The circuit of claim 5 , further comprising:

a third MOSFET device of a second conductivity type opposite the first conductivity type having a first conduction terminal connected to the gate terminal of the first MOSFET device, a second conduction terminal connected to the gate terminal of the second MOSFET device, and a gate terminal connected to the first power supply line; and

a fourth MOSFET device of said second conductivity type opposite the first conductivity type having a first conduction terminal connected to the gate terminal of the second MOSFET device, a second conduction terminal connected to the second power supply line, and a gate terminal connected to the gate terminal of the second MOSFET device.

7. The circuit of claim 1 , wherein the one or more trigger signals comprises a first trigger signal which is applied to the gate terminals of both the first and second MOSFET devices.

8. The circuit of claim 7 , further comprising a third MOSFET device of a second conductivity type opposite the first conductivity type having a first conduction terminal connected to the gate terminals of both the first and second MOSFET devices, a second conduction terminal connected to the second power supply line, and a gate terminal connected to the first power supply line.

9. The circuit of claim 1 , wherein the one or more trigger signals comprises a first trigger signal for application to gate terminal of the first MOSFET device and a second trigger signal, different from said first trigger signal, for application to the gate terminal of the second MOSFET device.

10. The circuit of claim 9 , further comprising:

a third MOSFET device of a second conductivity type opposite the first conductivity type having a first conduction terminal connected to the gate terminal of the first MOSFET device, a second conduction terminal connected to the gate terminal of the second MOSFET device, and a gate terminal connected to the first power supply line; and

a fourth MOSFET device of said second conductivity type opposite the first conductivity type having a first conduction terminal connected to the gate terminal of the second MOSFET device, a second conduction terminal connected to the second power supply line, and a gate terminal connected to the gate terminal of the second MOSFET device.

11. The circuit of claim 1 , further comprising a third MOSFET device of a second conductivity type opposite the first conductivity type having a first conduction terminal connected to the gate terminal of the first MOSFET device, a second conduction terminal connected to the gate terminal of the second MOSFET device, and a gate terminal connected to the first power supply line.

12. The circuit of claim 1 , further comprising a third MOSFET device of a second conductivity type opposite the first conductivity type having a first conduction terminal connected to the gate terminal of the second MOSFET device, a second conduction terminal connected to the second power supply line, and a gate terminal connected to the gate terminal of the second MOSFET device.

13. An electrostatic discharge (ESD) protection circuit, comprising:

a first power supply line;

a second power supply line;

a first MOSFET device;

a second MOSFET device;

wherein source-drain paths of the first and second MOSFET devices are connected in series between the first power supply line and the second power supply line;

a third MOSFET device having a first conduction terminal connected to gate terminals of both the first and second MOSFET devices, a second conduction terminal connected to the second power supply line, and a gate terminal connected to the first power supply line; and

a trigger circuit configured to generate, in response to detection of an ESD event at one or more of the first and second power supply lines, one or more trigger signals for application to the gate terminals of the first and second MOSFET devices.

14. The circuit of claim 13 , further comprising a functional circuit electrically coupled for power supply to the first and second power supply lines.

15. The circuit of claim 13 , wherein the trigger circuit comprises:

a resistive-capacitive ESD detection circuit configured to generate an ESD detection signal;

a first inverter circuit having an input coupled to receive the ESD detection signal; and

a second inverter circuit having an input coupled to an output of the first inverter circuit and an output configured to generate a first trigger signal of said one or more trigger signals which is applied to the gate terminals of both the first and second MOSFET devices.

16. The circuit of claim 13 , wherein the first and second MOSFET devices have a first conductivity type and the third MOSFET device has a second conductivity type opposite the first conductivity type.

17. An electrostatic discharge (ESD) protection circuit, comprising:

a first power supply line;

a second power supply line;

a first MOSFET device;

a second MOSFET device;

wherein source-drain paths of the first and second MOSFET devices are connected in series between the first power supply line and the second power supply line;

a third MOSFET device having a first conduction terminal connected to a gate terminal of the first MOSFET device, a second conduction terminal connected to a gate terminal of the second MOSFET device, and a gate terminal connected to the first power supply line;

a fourth MOSFET device having a first conduction terminal connected to the gate terminal of the second MOSFET device, a second conduction terminal connected to the second power supply line, and a gate terminal connected to the gate terminal of the second MOSFET device; and

a trigger circuit configured to generate, in response to detection of an ESD event at one or more of the first and second power supply lines, a first trigger signal for application to the gate terminal of the first MOSFET device and a second trigger and signal for application to the gate terminal of the second MOSFET devices.

18. The circuit of claim 17 , further comprising a functional circuit electrically coupled for power supply to the first and second power supply lines.

19. The circuit of claim 17 , wherein the first and second MOSFET devices have a first conductivity type and the third and fourth MOSFET devices have a second conductivity type opposite the first conductivity type.

20. An electrostatic discharge (ESD) protection circuit, comprising:

a first power supply line;

a second power supply line;

a first MOSFET device;

a second MOSFET device;

wherein source-drain paths of the first and second MOSFET devices are connected in series between the first power supply line and the second power supply line;

a third MOSFET device having a first conduction terminal connected to a gate terminal of the first MOSFET device, a second conduction terminal connected to a gate terminal of the second MOSFET device, and a gate terminal connected to the first power supply line; and

a trigger circuit configured to generate, in response to detection of an ESD event at one or more of the first and second power supply lines, a first trigger signal for application to the gate terminal of the first MOSFET device and a second trigger and signal for application to the gate terminal of the second MOSFET devices.

21. The circuit of claim 20 , further comprising a functional circuit electrically coupled for power supply to the first and second power supply lines.

22. The circuit of claim 20 , wherein the first and second MOSFET devices have a first conductivity type and the third MOSFET device has a second conductivity type opposite the first conductivity type.

23. An electrostatic discharge (ESD) protection circuit, comprising:

a first power supply line;

a second power supply line;

a first MOSFET device;

a second MOSFET device;

wherein source-drain paths of the first and second MOSFET devices are connected in series between the first power supply line and the second power supply line;

a third MOSFET device having a first conduction terminal connected to a gate terminal of the second MOSFET device, a second conduction terminal connected to the second power supply line, and a gate terminal connected to the gate terminal of the second MOSFET device; and

a trigger circuit configured to generate, in response to detection of an ESD event at one or more of the first and second power supply lines, a first trigger signal for application to the gate terminal of the first MOSFET device and a second trigger and signal for application to the gate terminal of the second MOSFET devices.

24. The circuit of claim 23 , further comprising a functional circuit electrically coupled for power supply to the first and second power supply lines.

25. The circuit of claim 23 , wherein the first and second MOSFET devices have a first conductivity type and the third MOSFET device has a second conductivity type opposite the first conductivity type.

Assignments (1)
CHANGE OF NAME Recorded Feb 23, 2024
From: STMICROELECTRONICS SA
To: STMICROELECTRONICS FRANCE
Reel/Frame 066663/0136 →
Continuity (2)
Division 15951806 · Apr 12, 2018
Related Publication 20200412124A1 · Dec 31, 2020