IP Library Granted Patent US 11,349,920
Granted Patent B2
US 11,349,920 · App. 17/015,764 · Granted May 31, 2022

Methods, devices and computer readable mediums for data synchronization

Inventors: Lifeng Yang (Beijing, CN); Jian Gao (Beijing, CN); Xinlei Xu (Beijing, CN); Ruiyong Jia (Beijing, CN); Yousheng Liu (Beijing, CN)
Assignee: EMC IP Holding Company LLC
H04L67/1095G06F15/17331G06F15/76H04L67/2842
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Quick Facts
Patent No.
US 11,349,920
App. No.
17/015,764
Granted
May 31, 2022
Kind
B2
Abstract

Embodiments of the present disclosure relate to methods, devices and computer readable mediums for data synchronization. A method comprises in response to receiving, at a first processor, a first request to synchronize data, initiating, to a second processor, a first remote direct memory access (RDMA) operation for transmitting the data between a first cache in the first processor and a second cache in the second processor. The method further comprises in response to completion of the first RDMA operation, writing the data into a first persistent storage device coupled to the first processor. The method further comprises transmitting, to the second processor, a command to instruct the second processor to commit the data to a second persistent storage device coupled to the second processor. Moreover, the method further comprises detecting, from the second processor, an acknowledgement for the command, the acknowledgement indicating that the data is synchronized between the first and second processors.

Claims (36)

1. A method of data synchronization, comprising:

in response to a first processor receiving a request to synchronize data, receiving, at a second processor, initiation of a first remote direct memory access (RDMA) operation from the first processor, the first RDMA operation including either an RDMA write operation that is configured to cause the data to be written from a first cache in the first processor into a second cache in the second processor, or an RDMA read operation that is configured to cause the data to be read from the second cache into the first cache;

in response to the first processor writing the data from the first cache into a first persistent storage device coupled to the first processor, receiving, from the first processor, a commit command configured to cause the second processor to write the data from the second cache to a second persistent storage device coupled to the second processor; and

in response to the commit command from the first processor, writing the data from the second cache into the second persistent storage device coupled to the second processor.

2. The method according to claim 1 , wherein the first RDMA operation is initiated via a network connecting the first and second processors, and the network is an Infiniband network.

3. The method according to claim 1 , wherein the first RDMA operation is an RDMA write operation and the data is transmitted via the RDMA write operation from the first cache in the first processor to the second cache in the second processor.

4. The method according to claim 2 , wherein the commit command is transmitted via a second RDMA operation and the second RDMA operation is initiated by the first processor via the network.

5. The method according to claim 1 , further comprising:

transmitting an acknowledgement for the first RDMA operation to the first processor.

6. The method according to claim 1 , further comprising:

transmitting an acknowledgement to the first processor, the acknowledgement indicating that the second processor has written the data from the second cache into the second persistent storage device.

7. The method according to claim 1 , wherein the second processor includes a central processing unit (CPU) which is constructed and arranged to execute a data storage operating system; and wherein the method further comprises:

receiving, as part of the first RDMA operation, the data into the second cache from the first processor without involvement of the CPU.

8. The method according to claim 1 , wherein the second processor includes a central processing unit (CPU) which is constructed and arranged to execute a data storage operating system; and wherein the method further comprises:

providing, as part of the first RDMA operation, the data from the second cache to the first processor without involvement of the CPU.

9. The method according to claim 1 , wherein the first processor and the second processor reside in different geographic areas and maintain respective copies of the same data to provide remote data mirroring over an Infiniband network.

10. A device for data synchronization, comprising:

at least one processing unit; and

at least one memory coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, the instructions, when executed by the at least one processing unit, causing the device to perform acts comprising:

in response to a first processor receiving a request to synchronize data, receiving initiation of a first remote direct memory access (RDMA) operation from the first processor, the first RDMA operation including either an RDMA write operation that is configured to cause the data to be written from a first cache in the first processor into a second cache of a second processor, or an RDMA read operation that is configured to cause the data to be read from the second cache into the first cache;

in response to the first processor writing the data from the first cache into a first persistent storage device coupled to the first processor, receiving, from the first processor, a commit command configured to cause the second processor to write the data to a second persistent storage device coupled to the second processor; and

in response to the commit command from the first processor, writing the data from the second cache into the persistent storage device coupled to the second processor.

11. The device according to claim 10 , wherein the first RDMA operation is initiated via a network connecting the first and second processors, and the network is an Infiniband network.

12. The device according to claim 10 , wherein the first RDMA operation is an RDMA write operation and the data is transmitted via the RDMA write operation from the first cache in the first processor to the second cache in the second processor.

13. The device according to claim 11 , wherein the commit command is transmitted via a second RDMA operation and the second RDMA operation is initiated by the first processor via the network.

14. The device according to claim 10 , wherein acts further include: transmitting an acknowledgement for the first RDMA operation to the first processor.

15. The device according to claim 10 , wherein acts further include: transmitting an acknowledgement to the first processor, the acknowledgement indicating that the second processor has written the data from the second cache into the second persistent storage device.

16. The device according to claim 10 , wherein the second processor includes a central processing unit (CPU) which is constructed and arranged to execute a data storage operating system; and wherein the acts further include: receiving, as part of the first RDMA operation, the data into the second cache from the first processor without involvement of the CPU.

17. The device according to claim 10 , wherein the second processor includes a central processing unit (CPU) which is constructed and arranged to execute a data storage operating system; and wherein the acts further include: providing, as part of the first RDMA operation, the data from the second cache to the first processor without involvement of the CPU.

18. A computer program product having a non-transitory computer readable medium which stores a set of instructions to perform data synchronization; the set of instructions, when carried out by a second processor, causing the second processor to perform a method of:

in response to a first processor receiving a request to synchronize data, receiving initiation of a first remote direct memory access (RDMA) operation from the first processor, the first RDMA operation including either an RDMA write operation that is configured to cause the data to be written from a first cache in the first processor into a second cache in the second processor, or an RDMA read operation that is configured to cause the data to be read from the second cache into the first cache;

in response to the first processor writing the data from the first cache into a first persistent storage device coupled to the first processor, receiving a commit command from the first processor, the commit command being configured to cause the second processor to write the data from the second cache into to a second persistent storage device coupled to the second processor; and

in response to the commit command from the first processor, writing the data from the second cache into to the second persistent storage device.

19. The computer program product according to claim 18 , wherein the method further includes: transmitting a first acknowledgement for the first RDMA operation to the first processor; and transmitting a second acknowledgement to the first processor, the second acknowledgement indicating that the second processor has written the data from the second cache into the second persistent storage device.

20. The computer program product according to claim 18 , wherein the second processor includes a central processing unit (CPU) which is constructed and arranged to execute a data storage operating system; and wherein the method further includes: receiving, as part of the first RDMA operation, the data into the second cache from the first processor without involvement of the CPU.

21. The computer program product according to claim 18 , wherein the second processor includes a central processing unit (CPU) which is constructed and arranged to execute a data storage operating system; and wherein the method further includes: providing, as part of the first RDMA operation, the data from the second cache to the first processor without involvement of the CPU.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (054475/0523) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: EMC IP HOLDING COMPANY LLC; DELL PRODUCTS L.P.
Reel/Frame 060332/0664 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (054475/0434) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: EMC IP HOLDING COMPANY LLC; DELL PRODUCTS L.P.
Reel/Frame 060332/0740 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (054475/0609) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: EMC IP HOLDING COMPANY LLC; DELL PRODUCTS L.P.
Reel/Frame 062021/0570 →
RELEASE OF SECURITY INTEREST AT REEL 054591 FRAME 0471 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058001/0463 →
SECURITY INTEREST Recorded Nov 18, 2020
From: EMC IP HOLDING COMPANY LLC; DELL PRODUCTS L.P.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 054475/0609 →
SECURITY INTEREST Recorded Nov 18, 2020
From: EMC IP HOLDING COMPANY LLC; DELL PRODUCTS L.P.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 054475/0434 →
SECURITY INTEREST Recorded Nov 18, 2020
From: EMC IP HOLDING COMPANY LLC; DELL PRODUCTS L.P.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 054475/0523 →
SECURITY AGREEMENT Recorded Nov 13, 2020
From: EMC IP HOLDING COMPANY LLC; DELL PRODUCTS L.P.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 054591/0471 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2020
From: YANG, LIFENG; GAO, JIAN; XU, XINLEI; JIA, RUIYONG; LIU, YOUSHENG
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 054138/0016 →