Selectable conversion ratio DC-DC converter
A single integrated circuit DC-to-DC conversion solution that can be used in conjunction with product designs requiring at least two different DC-to-DC conversion ratios, and in particular both divide-by-2 and divide-by-3 DC-to-DC buck conversion ratios or both multiply-by-2 and multiply-by-3 DC-to-DC boost conversion ratios. Embodiments are reconfigurable between a first Dickson converter configuration that includes at least two non-parallel capacitors (any of which may be off-chip) and associated controlled multi-phase switching to achieve a first conversion ratio, and a second Dickson converter configuration that includes a lesser equivalent number of capacitors than the first circuit configuration (which may be accomplished by parallelizing at least two non-parallel capacitors of the first configuration) and associated controlled multi-phase switching to achieve a second conversion ratio different from the first conversion ratio.
1. A DC-to-DC conversion circuit operable as a selectable conversion ratio Dickson converter circuit, including:
(a) a configurable clock signal control circuit that outputs a first phase clock signal, a second phase clock signal, and a selectable phase clock signal;
(b) at least one switch responsive to the first clock signal phase;
(c) at least one switch responsive to the second clock signal phase; and
(d) at least one switch responsive to the selectable phase clock signal;
wherein in a first circuit configuration for converting an applied input voltage to a first output voltage having a first conversion ratio with respect to the applied input voltage, the selectable phase clock signal is set to match phase only with the first phase clock signal, and
wherein in a second circuit configuration for converting the applied input voltage to a second output voltage having a second conversion ratio with respect to the applied input voltage, the selectable phase clock signal is set to match phase only with the second phase clock signal.
2. The invention of claim 1 , wherein the first clock signal phase and the second clock signal phase are generated by a two-phase clock and are non-overlapping.
3. The invention of claim 1 , wherein the first and second output voltages are less than the input voltage.
4. The invention of claim 1 , wherein the first and second output voltages are greater than the input voltage.
5. The invention of claim 1 , wherein the first conversion ratio and the second conversion ratio are integer-based ratios.
6. The invention of claim 1 , wherein the first conversion ratio is 3:1 and the second conversion ratio is 2:1.
7. The invention of claim 1 , wherein the DC-to-DC conversion circuit is fabricated as an integrated circuit.
8. A DC-to-DC conversion circuit operable as a selectable conversion ratio Dickson converter circuit, including:
(a) a configurable clock signal control circuit that outputs a first phase clock signal, a second phase clock signal, a selectable phase clock signal, and an inverted selectable clock signal;
(b) at least one switch responsive to the first clock signal phase;
(c) at least one switch responsive to the second clock signal phase; and
(d) at least one switch responsive to the selectable phase clock signal;
(e) at least one switch responsive to the inverted selectable phase clock signal;
wherein in a first circuit configuration for converting an applied input voltage to a first output voltage having a first conversion ratio with respect to the applied input voltage, the selectable phase clock signal is set to match phase only with the first phase clock signal and the inverted selectable phase clock signal is set to match phase only with the second phase clock signal, and
wherein in a second circuit configuration for converting the applied input voltage to a second output voltage having a second conversion ratio with respect to the applied input voltage, the selectable phase clock signal is set to match phase only with the second phase clock signal and the inverted selectable phase clock signal is set to match phase only with the first phase clock signal.
9. The invention of claim 8 , wherein the first clock signal phase and the second clock signal phase are generated by a two-phase clock and are non-overlapping.
10. The invention of claim 8 , wherein the first and second output voltages are less than the input voltage.
11. The invention of claim 8 , wherein the first and second output voltages are greater than the input voltage.
12. The invention of claim 8 , wherein the first conversion ratio and the second conversion ratio are integer-based ratios.
13. The invention of claim 8 , wherein the first conversion ratio is 3:1 and the second conversion ratio is 2:1.
14. The invention of claim 8 , wherein the DC-to-DC conversion circuit is fabricated as an integrated circuit.
15. A DC-to-DC conversion circuit, including:
(a) a configurable clock signal control circuit that outputs a first phase clock signal, a second phase clock signal, a selectable phase clock signal, and an inverted selectable phase clock signal;
(b) a first circuit configuration operable as a Dickson converter circuit for converting an applied input voltage to a first output voltage having a first conversion ratio with respect to the applied input voltage, the first circuit configuration having at least one switch responsive to the first clock signal phase, at least one switch responsive to the second clock signal phase, at least one switch responsive to the selectable phase clock signal, and at least one switch responsive to the inverted selectable phase clock signal; and
(c) a second circuit configuration operable as a Dickson converter circuit for converting the applied input voltage to a second output voltage having a second conversion ratio with respect to the applied input voltage, the second circuit configuration having at least one switch responsive to the first clock signal phase, at least one switch responsive to the second clock signal phase, at least one switch responsive to the selectable phase clock signal, and at least one switch responsive to the inverted selectable phase clock signal;
wherein in the first circuit configuration, the selectable phase clock signal is set to match phase only with the first phase clock signal and the inverted selectable phase clock signal is set to match phase only with the second phase clock signal, and wherein in the second circuit configuration, the selectable phase clock signal is set to match phase only with the second phase clock signal and the inverted selectable phase clock signal is set to match phase only with the first phase clock signal.
16. The invention of claim 15 , wherein the first clock signal phase and the second clock signal phase are generated by a two-phase clock and are non-overlapping.
17. The invention of claim 15 , wherein the first and second output voltages are less than the input voltage.
18. The invention of claim 15 , wherein the first and second output voltages are greater than the input voltage.
19. The invention of claim 15 , wherein the first conversion ratio and the second conversion ratio are integer-based ratios.
20. The invention of claim 15 , wherein the first conversion ratio is 3:1 and the second conversion ratio is 2:1.
21. The invention of claim 15 , wherein the DC-to-DC conversion circuit is fabricated as an integrated circuit.