Spread spectrum clock generation device and method for operating spread spectrum clock generation device

1. A device, comprising:

a clock delay circuit configured to receive a reference clock signal and generate N delay clock signals, where N is a natural number greater than or equal to 2, by using the reference clock signal; and

an output circuit configured to receive the N delay clock signals and output at least a portion of the delay clock signals from among the N delay clock signals as an output clock signal,

wherein a phase delay of a delay clock signal that is output later in time from among the at least the portion of the delay clock signals is greater than or equal to a phase delay of a delay clock signal that is output earlier in time, and

wherein the output circuit is configured to generate the output clock signal having a cycle equal to or longer than a cycle of the reference clock signal, such that none of cycles of the output clock signal is shorter than the cycle of the reference clock signal.

2. The device of claim 1 , wherein the clock delay circuit comprises N sub clock delay circuits connected in series.

3. The device of claim 1 , wherein the output circuit is configured to output only delay clock signals with a phase delay greater than or equal to 0 and less than 2π from among the at least the portion of the delay clock signals.

4. The device of claim 3 , wherein, in response to a delay clock signal to be output having a phase delay exceeding 2π, the output circuit is configured to output the reference clock signal instead of the delay clock signal to be output.

5. The device of claim 1 , further comprising a phase connection circuit configured to identify a delay clock signal having a phase delay exceeding 2π from among the N delay clock signals and generate a reference identifier in accordance with the identification result.

6. The device of claim 5 , wherein, on the basis of the reference identifier, the output circuit is configured to output only delay clock signals with a phase delay greater than or equal to 0 and less than 2π from among the at least the portion of the delay clock signals.

7. The device of claim 1 , wherein the output circuit comprises:

a memory comprising a profile used for identifying the at least the portion of the delay clock signals; and

an output module configured to select the at least the portion of the delay clock signals from among the N delay clock signals by using identifiers included in the profile.

8. The device of claim 7 , wherein the output module is configured to generate a count value, read an identifier corresponding to the count value by using the profile, and select the at least the portion of the delay clock signals by using the identifier.

9. The device of claim 1 , further comprising a compensation circuit configured to generate a compensation value such that the output clock signal corresponds to the reference clock signal, in response to the cycle of the output clock signal being less than the cycle of the reference clock signal.

10. A device, comprising:

a clock delay circuit configured to receive a reference clock signal and generate N delay clock signals, where N is a natural number greater than or equal to 2, by delaying sequentially the reference clock signal; and

an output circuit configured to receive the N delay clock signals, select a portion of the clock signals from among the N delay clock signals and the reference clock signal, and output the selected portion of the clock signals as an output clock signal in the order of smallest to largest phase delay,

wherein the output circuit is configured to generate the output clock signal having a cycle equal to or longer than a cycle of the reference clock signal, such that none of cycles of the output clock signal is shorter than the cycle of the reference clock signal.

11. The device of claim 10 , further comprising a phase connection circuit configured to detect phases of the N delay clock signals and generate a reference identifier for identifying a delay clock signal with a phase delay exceeding 2π from among the N delay clock signals.

12. The device of claim 11 , wherein, on the basis of the reference identifier, the output circuit outputs only clock signals with a phase delay greater than or equal to 0 and less than 2π from among the portion of the clock signals.

13. The device of claim 11 , wherein, on the basis of the reference identifier, the output circuit is configured to output a first clock signal having a small phase delay from among the reference clock signal or the portion of the clock signals, instead of a clock signal with a phase delay exceeding 2π, from among the portion of the clock signals.

14. The device of claim 10 , further comprising a compensation circuit configured to generate a compensation value such that the output clock signal corresponds to the reference clock signal, in response to the cycle of the output clock signal being less than the cycle of the reference clock signal.

15. A method for generating a spread spectrum clock signal, the method comprising:

receiving a reference clock signal;

generating N delay clock signals, where N is a natural number greater than or equal to 2, by using the reference clock signal; and

outputting sequentially at least a portion of the delay clock signals from among the N delay clock signals as an output clock signal,

wherein a phase delay of a delay clock signal that is output later in time among the at least the portion of the delay clock signals is greater than or equal to a phase delay of a delay clock signal that is output earlier in time, and

wherein the sequentially outputting comprises outputting the output clock signal having a cycle equal to or longer than a cycle of the reference clock signal, such that none of cycles of the output clock signal is shorter than the cycle of the reference clock signal.

16. The method of claim 15 , wherein the sequentially outputting comprises outputting only delay clock signals with a phase delay greater than or equal to 0 and less than 2π, from among the at least the portion of the delay clock signals.

17. The method of claim 15 , wherein the sequentially outputting comprises:

identifying an excess phase delay clock signal with a phase delay exceeding 2π from among the at least the portion of the delay clock signals; and

outputting a minimum phase delay clock signal having a minimum phase delay from among the reference clock signal and the at least the portion of the delay clock signals, instead of the excess phase delay clock signal.

18. The method of claim 15 , wherein the sequentially outputting comprises:

generating a count value in accordance with a cycle; and

outputting sequentially a delay clock signal corresponding to the count value from among the at least the portion of the delay clock signals.

19. A method for generating a spread spectrum clock signal, the method comprising:

receiving a reference clock signal;

generating N delay clock signals, where N is a natural number greater than or equal to 2, by delaying sequentially the reference clock signal;

receiving the N delay clock signals;

selecting a portion of the clock signals from among the N delay clock signals and the reference clock signal;

outputting sequentially the portion of the clock signals as an output clock signal in the order of smallest to largest phase delay,

wherein the sequentially outputting comprises outputting the output clock signal having a cycle equal to or longer than a cycle of the reference clock signal, such that none of cycles of the output clock signal is shorter than the cycle of the reference clock signal.

20. The method of claim 19 , further comprising detecting phases of the N delay clock signals and generate a reference identifier for identifying a delay clock signal with a phase delay exceeding 2π from among the N delay clock signals.

21. The method of claim 20 , further comprising, on the basis of the reference identifier, outputting a first clock signal having a small phase delay from among the reference clock signal or the portion of the clock signals, instead of a clock signal with a phase delay exceeding 2π, from among the portion of the clock signals.

22. The method of claim 20 , further comprising generating a compensation value, such that the output clock signal corresponds to the reference clock signal, in response to the cycle of the output clock signal being less than the cycle of the reference clock signal.