Volatile memory device with 3-D structure including memory cells having transistors vertically stacked one over another
Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes volatile memory cells located along a pillar that has a length extending in a direction perpendicular to a substrate of a memory device. Each of the volatile memory cells includes a capacitor and at least one transistor. The capacitor includes a capacitor plate. The capacitor plate is either formed from a portion a semiconductor material of the pillar or formed from a conductive material separated from the pillar by a dielectric.
1. An apparatus comprising:
a first data line and a second data line;
a first volatile memory cell including a first transistor coupled in series between the first and second data lines, and a first capacitor plate coupled in series with the first transistor between the first and second data lines; and
a second volatile memory cell including a second transistor coupled in series between the first and second data lines, and a second capacitor plate coupled in series with the second transistor between the first and second data lines, wherein the apparatus comprises a memory device, the memory device includes a substrate and a pillar extending perpendicular from the substrate, and wherein:
a first portion of the pillar forms part of the first capacitor plate; and
a second portion of the pillar forms part of the second capacitor plate, and the first and second capacitor plates are between the first and second data lines;
a third portion of the pillar forms part of a channel of the first transistor; and
a fourth portion of the pillar forms part of a channel of the second transistor, wherein the third and fourth portions are between the first and second portions, and, wherein the first and second portions include a semiconductor material of a first conductivity type, the third and fourth portions include a semiconductor material of a second conductivity type different from the first conductivity type.
2. The apparatus of claim 1 , wherein the first conductivity type includes n-type, and the second conductivity type includes p-type.
3. An apparatus comprising:
a first data line and a second data line;
a first volatile memory cell coupled to the first data line, the first data line configured to provide information to be stored in the first volatile memory cell;
a second volatile memory cell coupled to the second data line, the second data line configured to provide information to be stored in the second volatile memory cell; and
a switch coupled between the first and second volatile memory cells, the first and second volatile memory cells coupled in series with the switch between the first and second data lines, the switch configured to turn off during storing of the information in the first volatile memory cell, and to turn off during storing of the information in the second volatile memory cell, wherein:
the first volatile memory cell includes a first transistor coupled in series between the first data line and the switch, and a first capacitor plate located between the first transistor and the switch; and
the second volatile memory cell includes a second transistor coupled in series between the second data line and the switch, and a second capacitor plate located between the second transistor and the switch.
4. The apparatus of claim 3 , wherein the switch is configured to turn on during sensing of information stored in the first volatile memory cell and during sensing of information stored in the second volatile memory cell.
5. The apparatus of claim 3 , wherein the apparatus comprises a memory device, the memory device includes a substrate and a pillar extending perpendicular from the substrate, and wherein:
a first portion of the pillar forms part of a channel of the first transistor; and
a second portion of the pillar forms part of a channel of the second transistor.
6. The apparatus of claim 5 , wherein the switch includes a third transistor, and a third portion of the pillar between the first and second portions forms part of a channel of the third transistor.
7. The apparatus of claim 6 , wherein a fourth portion of the pillar between the first and third portions forms part of the first capacitor plate.
8. The apparatus of claim 7 , wherein a fifth portion of the pillar between the second and third portions forms part of the second capacitor plate.
9. The apparatus of claim 8 , wherein the first, second, and third portions include a semiconductor material of first conductivity type, the fourth and fifth portions include a semiconductor material of a second conductivity type different from the first conductivity type.
10. An apparatus comprising:
a first data line and a second data line;
a first volatile memory cell coupled to the first data line, the first data line configured to provide information to be stored in the first volatile memory cell;
a second volatile memory cell coupled to the second data line, the second data line configured to provide information to be stored in the second volatile memory cell; and
a switch coupled between the first and second volatile memory cells, the first and second volatile memory cells coupled in series with the switch between the first and second data lines, the switch configured to turn off during storing of the information in the first volatile memory cell, and to turn off during storing of the information in the second volatile memory cell, wherein:
the first data line is configured to receive a first voltage during sensing of information from each of the first and second volatile memory cells; and
a third data line is configured to receive a second voltage during sensing of information from each of the first and second volatile memory cells.
11. An apparatus comprising:
a first data line, a second data line, and a third data line;
a first volatile memory cell including first and second transistors coupled in series between the first and second data lines, and a first capacitor plate located between the first and second transistors; and
a second volatile memory cell including third and fourth transistors coupled in series between the second and third data lines, and a second capacitor plate located between the third and fourth transistors, wherein the first and second capacitor plates include a semiconductor material of a first conductivity type, and each of the first, second, third, and fourth transistors includes a channel having a semiconductor material of a second conductivity type different from the first conductivity type.
12. The apparatus of claim 11 , wherein:
the first data line is configured to provide information to be stored in the first volatile memory cell; and
the third data line configured to provide information to be stored in the second volatile memory cell.
13. The apparatus of claim 11 , wherein the apparatus comprises a memory device, the memory device includes a substrate and a pillar extending perpendicular from the substrate, and wherein:
a first portion of the pillar forms part of the channel of the first transistor;
a second portion of the pillar forms part of the channel of the second transistor;
a third portion of the pillar forms part of the channel of the third transistor; and
a fourth portion of the pillar forms part of the channel of the fourth transistor.
14. The apparatus of claim 13 , wherein a fifth portion of the pillar between the first and second portions forms part of the first capacitor plate.
15. The apparatus of claim 14 , wherein a sixth portion of the pillar between the third and fourth portions forms part of the second capacitor plate.
16. An apparatus comprising:
a first data line, a second data line, and a third data line;
a first volatile memory cell including first and second transistors coupled in series between the first and second data lines, and a first capacitor plate located between the first and second transistors; and
a second volatile memory cell including third and fourth transistors coupled in series between the second and third data lines, and a second capacitor plate located between the third and fourth transistors, wherein the first transistor has a longer channel length than the second transistor.