Semiconductor memory device

1. A semiconductor memory device comprising:

a memory cell array configured to include a first memory cell holding data of a first logic value and a second logic value, a plurality of second memory cells each holding data of the first logic value or the second logic value, two first bit lines connected to the first memory cell, and a plurality of second bit lines each connected to one of the plurality of second memory cells;

a plurality of pre-sense amplifiers, each configured to produce, in a read operation, an output potential obtained by resistively dividing a power supply voltage based on a potential of one of the two first bit lines or one of the plurality of second bit lines; and

a plurality of twin sense amplifiers, each configured to output data determination results based on two reference potentials and a data potential in the read operation, the two reference potentials being the output potentials produced based on the potentials of the two first bit lines, the data potential being the output potential produced based on the potential of one of the plurality of second bit lines.

2. The semiconductor memory device according to claim 1 , wherein:

each of the plurality of pre-sense amplifiers includes:

a p-channel field-effect transistor having a first gate connected to one of the two first bit lines or one of the plurality of second bit lines, a first source to which the power supply voltage is applied, and a first drain set at the produced output potential, and

an n-channel field-effect transistor having a second drain and a second gate connected to the first drain and a second source set at a ground potential.

3. The semiconductor memory device according to claim 1 , wherein:

each of the plurality of pre-sense amplifiers includes:

a p-channel field-effect transistor having a first source to which the power supply voltage is applied and a first drain and a first gate set at the produced output potential, and

an n-channel field-effect transistor having a second gate connected to one of the two first bit lines or one of the plurality of second bit lines, a second drain connected to the first drain and the first gate, and a second source set at a ground potential.

4. The semiconductor memory device according to claim 1 , wherein:

each of the plurality of pre-sense amplifiers includes:

a p-channel first field-effect transistor having a first gate connected to one of the two first bit lines or one of the plurality of second bit lines, a first source to which the power supply voltage is applied, and a first drain,

an n-channel second field-effect transistor having a second drain and a second gate connected to the first drain and a second source set at a ground potential,

a p-channel third field-effect transistor having a third source to which the power supply voltage is applied, and a third gate and a third drain set at the produced output potential, and

an n-channel fourth field-effect transistor having a fourth drain connected to the third gate and the third drain, a fourth gate connected to the first drain, the second drain, and the second gate, and a fourth source set at the ground potential.

5. The semiconductor memory device according to claim 1 , wherein:

each of the plurality of pre-sense amplifiers includes:

a p-channel first field-effect transistor having a first source to which the power supply voltage is applied, a first gate, and a first drain connected to the first gate,

an n-channel second field-effect transistor having a second drain connected to the first gate and the first drain, a second gate connected to one of the two first bit lines or one of the plurality of second bit lines, and a second source set at a ground potential,

a p-channel third field-effect transistor having a third source to which the power supply voltage is applied, a third gate connected to the first gate, the first drain, and the second drain, and a third drain set at the produced output potential, and

an n-channel fourth field-effect transistor having a fourth drain and a fourth gate connected to the third drain and a fourth source set at the ground potential.

6. The semiconductor memory device according to claim 1 , wherein:

the produced output potential is supplied to one of the plurality of twin sense amplifiers via one of fourth bit lines each connected to one of the plurality of pre-sense amplifiers.

7. The semiconductor memory device according to claim 6 , further comprising:

a plurality of pre-sense amplifier units, each configured to include the plurality of pre-sense amplifiers and share the fourth bit lines,

wherein the memory cell array includes a plurality of regions, in each of which the two first bit lines and the plurality of second bit lines are provided independently, and

the plurality of pre-sense amplifiers included in each of the plurality of pre-sense amplifier units is connected to the two first bit lines and the plurality of second bit lines provided in one of the plurality of regions.

8. The semiconductor memory device according to claim 1 , wherein:

each of the first memory cell and the plurality of second memory cells includes a ferroelectric capacitor.

9. The semiconductor memory device according to claim 1 , wherein:

the first memory cell is a 2T2C memory cell and the plurality of second memory cells are 1T1C memory cells.