Error correction circuit and operating method thereof

1. An error correction circuit comprising:

a first error correction encoder configured to generate a plurality of row-codewords by performing first error correction encoding on each of a plurality of messages;

a second error correction encoder configured to organize m-bit symbols by grouping p-bit symbols in each of row-codewords in a unit of a column layer including m columns, and generate a plurality of column-codewords by performing second error correction encoding on each of symbol groups configured with m-bit symbols belonging to the same column layer among the m-bit symbols, where each of p and m is a natural number;

a first error correction decoder configured to perform first error correction decoding on each of read row-vectors corresponding to the plurality of row-codewords, and output soft information of the first error correction decoding, corresponding to each of p-bit symbols in each of read row-vectors on which the first error correction decoding fails; and

a second error correction decoder configured to determine whether each of m-bit symbols in read column-vectors corresponding to the column-codewords is reliable, based on the soft information corresponding to each of the p-bit symbols, and perform second error correction decoding on the read column-vectors, based on the determination of whether each of the m-bit symbols is reliable.

2. The error correction circuit of claim 1 , wherein the soft information of the first error correction decoding includes a flipping function value of a variable node corresponding to each of the p-bit symbols in the read row-vectors.

3. The error correction circuit of claim 1 , wherein the soft information of the first error correction decoding includes a posteriori probability (APP) of a variable node corresponding to each of the p-bit symbols in the read row-vectors.

4. The error correction circuit of claim 1 , wherein, when the first error correction decoding performed by the first error correction decoder succeeds, a target row-codeword decoded by the first error correction decoder is output.

5. The error correction circuit of claim 1 , wherein the second error correction decoder performs the second error correction decoding by setting an m-bit symbol, which is determined to be reliable, among the m-bit symbols, as a non-error symbol.

6. The error correction circuit of claim 1 , wherein the second error correction decoder determines that the m-bit symbol is reliable, when a reliability of select p-bit symbols is greater than or equal to a set value, the number of the select p-bit symbols being greater than or equal to a set number, among the p-bit symbols in the m-bit symbol.

7. The error correction circuit of claim 1 , wherein the first error correction decoder performs the first error correction decoding on a read row-vector including p-bit symbols in an m-bit symbol corrected by the second error correction decoding among the read row-vectors on which the first error correction decoding fails.

8. The error correction circuit of claim 1 , wherein each of the column-codewords is a codeword of a maximum distance separable (MDS) code.

9. The error correction circuit of claim 8 , wherein the second error correction decoding includes at least one of error decoding and erasure decoding.

10. The error correction circuit of claim 9 , wherein, when a number of m-bit symbols determined as unreliable symbols among the m-bit symbols in each of the read column-vectors is less than or equal to A as an erasure correction capability of the MDS code, the second error correction decoder performs the erasure decoding on the read column-vector, where A is a natural number.

11. The error correction circuit of claim 9 , wherein, when a number of m-bit symbols determined as unreliable symbols among the m-bit symbols in each of the read column-vectors is less than or equal to B as an error correction capability of the MDS code, the second error correction decoder performs the error decoding on the read column-vector, where B is a natural number.

12. A method for operating an error correction circuit, the method comprising:

generating a plurality of row-codewords by performing first error correction encoding on each of a plurality of messages;

organizing m-bit symbols by grouping p-bit symbols in each of row-codewords in a unit of a column layer including m columns, where each of p and m is a natural number;

generating a plurality of column-codewords by performing second error correction encoding on each of symbol groups configured with m-bit symbols belonging to the same column layer among the m-bit symbols;

performing first error correction decoding on each of read row-vectors corresponding to the plurality of row-codewords;

determining whether each of m-bit symbols in read column-vectors corresponding to the column-codewords is reliable, based on soft information of the first error correction decoding, which corresponds to each of p-bit symbols in each of read row-vectors on which the first error correction decoding fails; and

performing second error correction decoding on the read column-vectors, based on the determination of whether each of the m-bit symbols is reliable.

13. The method of claim 12 , wherein the soft information of the first error correction decoding includes a flipping function value of a variable node corresponding to each of the p-bit symbols in the read row-vectors.

14. The method of claim 12 , wherein the soft information of the first error correction decoding includes a posteriori probability (APP) of a variable node corresponding to each of the p-bit symbols in the read row-vectors.

15. The method of claim 12 , wherein the performing of the second error correction decoding includes performing the second error correction decoding by setting an m-bit symbol, which is determined to be reliable, among the m-bit symbols, as a non-error symbol.

16. The method of claim 12 , wherein the determining of whether each of the m-bit symbols is reliable includes determining that the m-bit symbol is reliable when a reliability of p-bit symbols, the number of which is greater than or equal to a set number, among the p-bit symbols in the m-bit symbol, is greater than or equal to a set value.

17. The method of claim 12 , further comprising performing the first error correction decoding on a read row-vector including p-bit symbols in an m-bit symbol corrected by the second error correction decoding among the read row-vectors on which the first error correction decoding fails.

18. The method of claim 12 , wherein each of the column-codewords is a codeword of a maximum distance separable (MDS) code.

19. The method of claim 18 , wherein the second error correction decoding includes at least one of error decoding and erasure decoding.

20. The method of claim 19 , wherein the performing of the second error correction decoding includes performing the erasure decoding on the read column-vector, when a number of m-bit symbols determined to be unreliable, among the m-bit symbols in each of the read column-vectors, is less than or equal to A as an erasure correction capability of the MDS code, where A is a natural number.

21. The method of claim 19 , wherein the performing of the second error correction decoding includes performing the error decoding on the read column-vector, when a number of m-bit symbols determined as unreliable symbols among the m-bit symbols in each of the read column-vectors is less than or equal to B as an error correction capability of the MDS code, where B is a natural number.