System with cache-coherent memory and server-linking switch
A system and method for managing memory resources. In some embodiments the system includes a first server, a second server, and a server-linking switch connected to the first server and to the second server. The first server may include a stored-program processing circuit, a cache-coherent switch, and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, the cache-coherent switch is connected to the server-linking switch, and the stored-program processing circuit is connected to the cache-coherent switch.
1. A system, comprising:
a first server, comprising:
a stored-program processing circuit,
a cache-coherent switch, and
a first memory module; and
a second server; and
a server-linking switch connected to the first server and to the second server,
wherein:
the first memory module is connected to the cache-coherent switch via a first interface,
the cache-coherent switch is connected to the server-linking switch, and
the stored-program processing circuit is connected to the cache-coherent switch via a second interface different from the first interface.
2. The system of claim 1 , wherein the server-linking switch comprises a Peripheral Component Interconnect Express (PCIe) switch.
3. The system of claim 1 , wherein the server-linking switch comprises a Compute Express Link (CXL) switch.
4. The system of claim 3 , wherein the server-linking switch comprises a top of rack (ToR) CXL switch.
5. The system of claim 1 , wherein the server-linking switch is configured to discover the first server.
6. The system of claim 1 , wherein the server-linking switch is configured to cause the first server to reboot.
7. The system of claim 1 , wherein the server-linking switch is configured to cause the cache-coherent switch to disable the first memory module.
8. The system of claim 1 , wherein the server-linking switch is configured to transmit data from the second server to the first server, and to perform flow control on the data.
9. The system of claim 1 , further comprising a third server connected to the server-linking switch, wherein:
the server-linking switch is configured to:
receive a first packet, from the second server,
receive a second packet, from the third server, and
transmit the first packet and the second packet to the first server.
10. The system of claim 1 , further comprising a second memory module connected to the cache-coherent switch, wherein the first memory module comprises volatile memory and the second memory module comprises persistent memory.
11. The system of claim 10 , wherein the cache-coherent switch is configured to virtualize the first memory module and the second memory module.
12. The system of claim 11 , wherein the first memory module comprises flash memory, and the cache-coherent switch is configured to provide a flash translation layer for the flash memory.
13. The system of claim 1 , wherein the first server comprises an expansion socket adapter, connected to an expansion socket of the first server, the expansion socket adapter comprising:
the cache-coherent switch; and
a memory module socket,
the first memory module being connected to the cache-coherent switch through the memory module socket.
14. The system of claim 13 , wherein the memory module socket comprises an M.2 socket.
15. The system of claim 13 , wherein:
the cache-coherent switch is connected to the server-linking switch through a connector, and
the connector is on the expansion socket adapter.
16. A method for performing remote direct memory access in a computing system, the computing system comprising:
a first server,
a second server,
a third server, and
a server-linking switch connected to the first server, to the second server, and to the third server,
the first server comprising:
a stored-program processing circuit,
a cache-coherent switch, and
a first memory module, wherein the first memory module is connected to the cache-coherent switch via a first interface, and the stored-program processing circuit is connected to the cache-coherent switch via a second interface different from the first interface,
the method comprising:
receiving, by the server-linking switch, a first packet, from the second server,
receiving, by the server-linking switch, a second packet, from the third server, and
transmitting the first packet and the second packet to the first server.
17. The method of claim 16 , further comprising:
receiving, by the cache-coherent switch, a remote direct memory access (RDMA) request, and
sending, by the cache-coherent switch, a RDMA response.
18. The method of claim 17 , wherein the receiving of the RDMA request comprises receiving the RDMA request through the server-linking switch.
19. The method of claim 17 , further comprising:
receiving, by the cache-coherent switch, a read command, from the stored-program processing circuit, for a first memory address,
translating, by the cache-coherent switch, the first memory address to a second memory address, and
retrieving, by the cache-coherent switch, data from the first memory module at the second memory address.
20. A system, comprising:
a first server, comprising:
a stored-program processing circuit,
cache-coherent switching means,
a first memory module; and
a second server; and
a server-linking switch connected to the first server and to the second server,
wherein:
the first memory module is connected to the cache-coherent switching means via a first interface,
the cache-coherent switching means is connected to the server-linking switch, and
the stored-program processing circuit is connected to the cache-coherent switching means via a second interface different from the first interface.