IP Library Granted Patent US 11,593,202
Granted Patent B2
US 11,593,202 · App. 17/027,301 · Granted Feb 28, 2023

Data processing system, memory controller therefor, and operating method thereof

Inventor: Kyu Hyun Choi (Icheon, KR)
Assignee: SK Hynix Inc.
G06F11/1076G06N3/08G06F11/1004G06F11/1012G06F11/1068G11C11/5628G11C16/26G11C29/42H04L1/0072H04L1/0083
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Quick Facts
Patent No.
US 11,593,202
App. No.
17/027,301
Granted
Feb 28, 2023
Kind
B2
Abstract

A data processing system may include a memory module; and a controller configured to exchange data with the memory module in response to a request received from a host. The controller divide a first data into a first data group to error correction and a second data group not to error correction in response to the first data and a first data write request received from the host, generates a first meta data for error correction for the first data group, configures a first data chunk that includes the first data and the first meta data, and transmits the first data chunk to the memory module.

Claims (64)

1. A data processing system, comprising:

a memory module; and

a controller configured to exchange data with the memory module in response to a request received from a host,

wherein the controller is configured to:

divide a first data into a first data group which is a set number of upper bits of the first data and is for error correction and a second data group which is at least part of the first data excluding the first data group and is not for error correction in response to the first data and a first data write request received from the host;

generate a first meta data for error correction for the first data group based on the first data group;

configure a first data chunk that including the first data and the first meta data; and

transmit the first data chunk to the memory module.

2. The data processing system of claim 1 , wherein the controller is configured to:

receive the first data chunk from the memory module in response to a first data read request received from the host;

generate a first read data by correcting an error of the first data group based on the first meta data; and

transmit the first read data to the host.

3. The data processing system of claim 1 , wherein the first data group comprises a first sub-data group and a second sub-data group.

4. The data processing system of claim 3 , wherein the first meta data comprises a first sub-meta data for the first sub-data group and a second sub-meta data for the second sub-data group.

5. The data processing system of claim 1 , wherein the controller is further configured to control the second data group not to be used during the generation of the first meta data.

6. The data processing system of claim 1 , wherein the first data corresponding to first data write request is a data for an artificial intelligence application processing including a neural network operation.

7. The data processing system of claim 6 , wherein:

the first data corresponding to first data write request is an integer of a weight used in the neural network operation.

8. The data processing system of claim 1 , wherein the controller is configured to:

generate a second meta data for error correction with respect to a second data in response to the second data and a second data write request received from the host;

configure a second data chunk that includes the second data and the second meta data; and

transmit the second data chunk to the memory module.

9. The data processing system of claim 8 , wherein the controller is configured to:

receive the second data chunk from the memory module in response to a second data read request received from the host;

generate a second read data by correcting an error of the second data based on the second meta data; and

transmit the second read data to the host.

10. A memory controller configured to exchange data with a memory module in response to a request received from a host, the memory controller configured to:

perform an error check and correction operation by:

generating a meta data based on a data received from the host; and

transmitting, to the memory module, a data chunk that includes the data and the meta data to store the data chunk in the memory module;

wherein the data includes:

a first part, which is a set number of upper bits of the data and is used to generate the meta data used for error correction; and

a second part, which is at least part of the data excluding the first part, that is not used to generate the meta data used for error correction when an operation mode of the memory controller is a first operation mode and that is used to generate the meta data used for error correction when the operation mode of the memory controller is a second operation mode.

11. The memory controller of claim 10 , wherein the memory controller is further configured to:

set the operation mode of the memory controller to the first operation mode or the second operation mode based on a type of application for which processing has been requested by the host;

perform the error check and correction operation based on the set operation mode and in response to the request received from the host;

transmit a command to the memory module; and

perform the error check and correction operation based on a first meta data for the first part of the data when the operation mode of the memory controller is set to the first operation mode.

12. The memory controller of claim 11 , wherein the memory controller is further configured to, when the operation mode of the memory controller is configured to the second operation mode, perform the error check and correction operation based on a second meta data for the data including the first part and the second part.

13. The memory controller of claim 11 , wherein the first operation mode is an artificial intelligence application processing mode including a neural network operation.

14. The memory controller of claim 13 , wherein:

the first part is an integer part of a weight used in the neural network operation.

15. The memory controller of claim 10 , wherein the first part comprises a first sub-data group and a second sub-data group.

16. The memory controller of claim 15 , wherein the first meta data comprises a first sub-meta data for the first sub-data group and a second sub-meta data for the second sub-data group.

17. A method of operating a memory controller that exchanges data with a memory module in response to a request received from a host, the method comprising:

dividing, by the memory controller, a first data into a first data group which is a set number of upper bits that form the first data and is for error correction and a second data group which is at least part of the first data excluding the first data group and is not for error correction in response to the first data and a first data write request received from the host;

generating, by the memory controller, a first meta data for error correction for the first data group based on the first data group; and

transmitting, by the memory controller, to the memory module, a first data chunk that includes the first data and the first meta data.

18. The method of claim 17 , further comprising:

receiving the first data chunk from the memory module when a first read request for the first data is received from the host;

generating a first read data by correcting an error of the first data group based on the first meta data; and

transmitting the first read data to the host.

19. The method of claim 17 , further comprising:

generating a second meta data for error correction using a second data in response to the second data and a second data write request received from the host; and

transmitting, to the memory module, a second data chunk that includes the second data and the second meta data.

20. The method of claim 19 , further comprising:

receiving the second data chunk from the memory module when a second read request for the second data is received from the host;

generating the second read data by correcting an error of the second data based on the second meta data; and

transmitting the read data to the host.

21. The operating method of claim 17 , wherein:

the first data group comprises a first sub-data group and a second sub-data group; and

generating the first meta data for error correction includes generating a first sub-meta data for the first sub-data group and a second sub-meta data for the second sub-data group.

22. The method of claim 17 , wherein the generated first meta data does not include the second data group of the first data.

23. The operating method of claim 17 , wherein the data corresponding to the first data write request is a data for an artificial intelligence application processing mode including a neural network operation.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2024
From: SK HYNIX INC.
To: MIMIRIP LLC
Reel/Frame 067335/0246 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2020
From: CHOI, KYU HYUN
To: SK HYNIX INC.
Reel/Frame 053845/0433 →