Semiconductor memory subword driver circuits and layout
In some examples, a subword driver block of a memory device includes a first active region and a second active region adjacent to each other. The first active region forms drains/sources of a first and second transistors in a first region; the second active region forms drains/sources of a third and fourth transistors in a second region, where the first and second regions are adjacent to each other. The first, second, third and fourth transistors are coupled to a common non-active potential via a shared contact overlaid over a merged region between the first and second regions. The first and second active regions may comprise N+ diffusion materials.
1. A semiconductor device comprising:
a first area of a subword driver block, the first area comprising:
a first active region on which a first transistor and a second transistor are formed, the first active region extending in a first direction, the first and second transistors coupled to different main word lines;
a second active region on which a third transistor and a fourth transistor are formed, the second active region extending in the first direction;
a fifth transistor coupled to the first transistor;
a sixth transistor coupled to the third transistor, the fifth transistor coupled to a first word driver line, the sixth transistor coupled to a second word driver line different from the first word driver line;
a diffusion region configured to merge the first and second active regions; and
a contact on the first active region between the first transistor and the second transistor in a second direction that is perpendicular to the first direction and coupled to a non-active potential,
wherein third and fourth transistors are coupled to the non-active potential via the contact and the diffusion region.
2. The semiconductor device of claim 1 , wherein the diffusion region is merged with drains/sources of the first, second, third and fourth transistors.
3. The semiconductor device of claim 1 , wherein the contact is coupled to the drains/sources of the first and second transistors.
4. The semiconductor device of claim 3 , wherein the drains/sources of the first and second transistors are coupled to output of first and second subword drivers, respectively.
5. The semiconductor device of claim 4 , wherein the sources/drains of the first and second transistors are further coupled to first and second word lines of a memory cell array, respectively.
6. The semiconductor device of claim 1 further comprising:
a first gate electrode, wherein the first gate electrode overlaps with the first and second active regions to form the first and third transistors; and
a second gate electrode, wherein the second gate electrode overlaps with the first and second active regions to form the second and fourth transistors.
7. The semiconductor device of claim 6 , wherein the first gate electrode is coupled to a first main word line of the different main word lines and the second gate electrode is coupled to a second main word line of the different main word lines.
8. The semiconductor device of claim 7 , wherein the first, second, third and fourth transistors are of a first conductivity type.
9. The semiconductor device of claim 1 further comprising first and second interconnections and a wiring in-between the first and second interconnections, wherein the wiring is coupled to the contact.
10. The semiconductor device of claim 9 , wherein the first and second interconnections are configured to form a recess in-between to accommodate the wiring.
11. The semiconductor of claim 10 further comprising a second area of a subword driver block, the second area adjacent to the first region and comprising:
one or more active regions; and
a plurality of transistors formed on the one or more active regions and a respective gate electrode of a plurality of gate electrodes,
wherein the plurality of transistors are of a second conductivity type.
12. The semiconductor device of claim 9 , wherein the first and second active regions extend along a first direction and the first and second interconnections extend along a second direction substantially perpendicular to the first direction.
13. A semiconductor device comprising:
a first area of a subword driver block, the first area comprising:
a first active region extending in a first direction and having a first portion, on which a first transistor and a second transistor are formed, and a second portion, the second portion being narrower than the first portion, the first and second transistors coupled to different main word lines;
a second active region extending in a first direction and having a third portion, on which a third transistor and a fourth transistor are formed, and a fourth portion, the fourth portion being narrower than the third portion;
a fifth transistor coupled to the first transistor;
a sixth transistor coupled to the third transistor, the fifth transistor coupled to a first word driver line, the sixth transistor coupled to a second word driver line different from the first word driver line;
a diffusion region connecting the first portion and the third portion and configured to merge the first and second active regions; and
a contact on the first active region between the first transistor and the second transistor in a second direction that is perpendicular to the first direction and coupled to a non-active potential,
wherein third and fourth transistors are coupled to the non-active potential via the contact and the diffusion region.
14. The semiconductor device of claim 13 , wherein the diffusion region is merged with drains/sources of the first, second, third and fourth transistors.
15. The semiconductor device of claim 13 , wherein the contact is coupled to the drains/sources of the first and second transistors.
16. The semiconductor device of claim 15 , wherein the drains/sources of the first and second transistors are coupled to output of first and second subword drivers, respectively.
17. The semiconductor device of claim 16 , wherein the sources/drains of the first and second transistors are further coupled to first and second word lines of a memory cell array, respectively.
18. The semiconductor device of claim 13 further comprising:
a first gate electrode, wherein the first gate electrode overlaps with the first and second active regions to form the first and third transistors; and
a second gate electrode, wherein the second gate electrode overlaps with the first and second active regions to form the second and fourth transistors.
19. The semiconductor device of claim 18 , wherein the first gate electrode is coupled to a first main word line of the different main word lines and the second gate electrode is coupled to a second main word line of the different main word lines.
20. The semiconductor device of claim 19 , wherein the first, second, third and fourth transistors are of a first conductivity type.
21. The semiconductor device of claim 13 further comprising first and second interconnections and a wiring in-between the first and second interconnections, wherein the wiring is coupled to the contact.
22. The semiconductor device of claim 21 , wherein the first and second interconnections are configured to form a recess in-between to accommodate the wiring.
23. The semiconductor of claim 22 further comprising a second area of a subword driver block, the second area adjacent to the first region and comprising:
one or more active regions; and
a plurality of transistors formed on the one or more active regions and a respective gate electrode of a plurality of gate electrodes,
wherein the plurality of transistors are of a second conductivity type.
24. The semiconductor device of claim 21 , wherein the first and second active regions extend along a first direction and the first and second interconnections extend along a second direction substantially perpendicular to the first direction.