Structure and method to provide conductive field plate over gate structure
Embodiments of the disclosure provide an integrated circuit device and related methods. The disclosure may provide a transistor device, including: a gate structure; a drain extension region extending laterally from partially under the gate structure to a drain region; and a gate spacer located over the drain extension region. A silicide-blocking layer is over and in contact with the gate spacer. The silicide-blocking layer has a first end over the gate structure and a second, opposing end over the drain extension region. The structure also provides a conductive field plate, including a conductive layer over and in contact with the silicide-blocking layer. A field plate contact is formed on the conductive field plate.
1. An integrated circuit device, comprising:
a transistor device, including:
a gate structure;
a drain extension region extending laterally from partially under the gate structure to a drain region; and
a gate spacer located over the drain extension region;
a silicide-blocking layer over and contacting the gate spacer, the silicide-blocking layer having a first end over the gate structure and a second, opposing end over the drain extension region;
a conductive field plate, including a conductive layer over and in contact with the silicide-blocking layer; and
an isolation region within the drain extension region, wherein the isolation region extends from beneath the gate structure to beneath the conductive field plate; and
a field plate contact on the conductive field plate.
2. The integrated circuit device of claim 1 , wherein the conductive layer includes silicon.
3. The integrated circuit device of claim 1 , wherein the conductive layer includes silicide.
4. The integrated circuit device of claim 1 , wherein the conductive layer includes metal.
5. The integrated circuit device of claim 1 , further comprising:
a conductive region on the field plate contact; and
a source contact extending from the conductive region to a source region of the transistor device.
6. The integrated circuit device of claim 1 , wherein a portion of the gate structure is over the drain extension region, and wherein the portion is at most approximately 0.5 micrometers in horizontal length.
7. The integrated circuit device of claim 1 , wherein the silicide-blocking layer includes a dielectric.
8. The integrated circuit device of claim 1 , further comprising a gate dielectric layer under the gate structure and over the drain extension region.
9. The integrated circuit device of claim 8 , wherein the gate dielectric layer is thicker over the drain extension region.
10. The integrated circuit device of claim 8 , wherein the silicide-blocking layer is over and contacting the gate dielectric layer.
11. A conductive field plate, comprising:
a silicide-blocking layer over and contacting a gate spacer of a transistor device, the silicide-blocking layer over an isolation region within a drain extension region of the transistor device, wherein the isolation region extends from beneath a gate structure of the transistor device to beneath the conductive field plate;
a conductive layer over and contacting the silicide-blocking layer;
a field plate contact on the conductive layer; and
a conductive region over the conductive layer, wherein the field plate contact electrically couples the conductive region to the conductive layer, and wherein a source contact electrically couples the conductive region to a source region of the transistor device.
12. The conductive field plate of claim 11 , wherein the conductive layer includes silicide.
13. The conductive field plate of claim 11 , wherein the conductive layer includes silicon.
14. The conductive field plate of claim 11 , wherein the conductive layer includes metal.
15. The conductive field plate of claim 11 , wherein the silicide-blocking layer includes a first end over a gate structure of the transistor device and a second, opposing end over a drain extension region of the transistor device.
16. A method of forming an integrated circuit device, comprising:
forming a transistor device, including:
a gate structure;
a drain extension region extending laterally from partially under the gate structure to a drain region; and
a gate spacer located over the drain extension region;
forming a silicide-blocking layer over and in contact with the gate spacer, the silicide-blocking layer having a first end over the gate structure and a second, opposing end over the drain extension region;
forming a conductive field plate on and in contact with the silicide-blocking layer;
forming an isolation region within the drain extension region, wherein the isolation region extends from beneath the gate structure to beneath the conductive field plate; and
forming a field plate contact to the conductive field plate.
17. The method of claim 16 , wherein the conductive field plate includes a conductive layer and a silicide layer.
18. The method of claim 17 , wherein the conductive layer includes silicide.
19. The method of claim 16 , further comprising:
forming a gate dielectric layer under the gate structure and over the drain extension region.
20. The method of claim 19 , wherein the gate dielectric layer is thicker over the drain extension region.