Method and apparatus for reducing the latency of long latency memory requests
Systems, apparatuses, and methods for efficiently processing memory requests are disclosed. A computing system includes at least one processing unit coupled to a memory. Circuitry in the processing unit determines a memory request becomes a long-latency request based on detecting a translation lookaside buffer (TLB) miss, a branch misprediction, a memory dependence misprediction, or a precise exception has occurred. The circuitry marks the memory request as a long-latency request such as storing an indication of a long-latency request in an instruction tag of the memory request. The circuitry uses weighted criteria for scheduling out-of-order issue and servicing of memory requests. However, the indication of a long-latency request is not combined with other criteria in a weighted sum. Rather, the indication of the long-latency request is a separate value. The circuitry prioritizes memory requests marked as long-latency requests over memory requests not marked as long-latency requests.
1. An apparatus comprising:
a queue comprising a first memory request with a first priority and a second memory request with a second priority higher than the first priority; and
circuitry configured to:
store an indication that the first memory request is a long-latency request, based at least in part on execution of the first memory request causing a page table walk; and
cause the first memory request to issue prior to the second memory request, responsive to the indication that the first memory request is a long-latency request.
2. The apparatus as recited in claim 1 , wherein the circuitry is further configured to mark, for issue, the first memory request prior to marking for issue memory requests in the queue that are not identified as long-latency requests.
3. The apparatus as recited in claim 1 , wherein the circuitry is configured to store the indication in an instruction tag of the first memory request.
4. The apparatus as recited in claim 1 , wherein the circuitry is further configured to store an indication that a given memory request is a long-latency request, responsive to the given memory request being included in an alternate path of instructions fetched from an instruction cache into a processor pipeline after a mispredicted branch operation is detected and resolved.
5. The apparatus as recited in claim 1 , wherein:
the apparatus further comprises a second queue configured to store read responses; and
the circuitry is further configured to identify one or more read responses as long-latency responses based on a detection that the one or more read responses correspond to long-latency requests.
6. The apparatus as recited in claim 5 , wherein the circuitry is further configured to service one or more read requests with one or more read responses identified as long-latency responses before servicing any read requests with read responses not identified as long-latency read responses.
7. The apparatus as recited in claim 5 , wherein the circuitry is further configured to mark, for issue, one or more long-latency read responses before marking, for issue, any read responses not identified as long-latency read responses.
8. A method, comprising:
storing, in a queue, a first memory request with a first priority and a second memory request with a second priority higher than the first priority;
storing, by circuitry, an indication that the first memory request is a long-latency request, based at least in part on execution of the first memory request causing a page table walk; and
causing, by the circuitry, the first memory request to issue prior to the second memory request, responsive to the indication that the first memory request is a long-latency request.
9. The method as recited in claim 8 , further comprising marking, for issue, the first memory request prior to marking for issue memory requests in the queue that are not identified as long-latency requests.
10. The method as recited in claim 8 , further comprising storing the indication in an instruction tag of the first memory request.
11. The method as recited in claim 8 , further comprising storing an indication that a given memory request is a long-latency request, responsive to the given memory request being included in an alternate path of instructions fetched from an instruction cache into a processor pipeline after a mispredicted branch operation is detected and resolved.
12. The method as recited in claim 8 , wherein:
storing, in a second queue, read responses; and
identifying one or more read responses as long-latency responses based on a detection that the one or more read responses correspond to long-latency requests.
13. The method as recited in claim 12 , further comprising servicing one or more read requests with one or more read responses identified as long-latency responses before servicing any read requests with read responses not identified as long-latency read responses.
14. The method as recited in claim 12 , further comprising marking, for issue, one or more long-latency read responses before marking, for issue, any read responses not identified as long-latency read responses.
15. A computing system comprising:
a processor core configured to generate memory requests;
a controller configured to:
store, in a queue, a first memory request with a first priority and a second memory request with a second priority higher than the first priority;
store an indication that the first memory request is a long-latency request, based at least in part on execution of the first memory request causing a page table walk; and
cause the first memory request to issue prior to the second memory request, responsive to the indication that the first memory request is a long-latency request.
16. The computing system as recited in claim 15 , wherein the controller is further configured to mark, for issue, the first memory request prior to marking for issue memory requests in the queue that are not identified as long-latency requests.
17. The computing system as recited in claim 15 , wherein the first memory request is a replay memory request.
18. The computing system as recited in claim 15 , wherein the controller is further configured to store an indication that a given memory request is a long-latency request, responsive to the given memory request being included in an alternate path of instructions fetched from an instruction cache into a processor pipeline after a mispredicted branch operation is detected and resolved.
19. The computing system as recited in claim 15 , wherein:
the controller further comprises a second queue configured to store read responses; and
the controller is further configured to identify one or more read responses as long-latency responses based on a detection that the one or more read responses correspond to long-latency requests.
20. The computing system as recited in claim 19 , wherein the controller is further configured to service one or more read requests with one or more read responses identified as long-latency responses before servicing any read requests with read responses not identified as long-latency read responses.