ESD PROTECTION FOR INTEGRATED CIRCUIT DEVICES
An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include electrostatic discharge (ESD) protection circuit structures. The ESD protection circuit structures may be formed in regions other than the region that the IGFETs are formed as well as in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming ESD protection circuit structures in regions below the IGFETs, an older process technology may be used and device size may be decreased. Furthermore, planar IGFETs of FinFETs may be formed in other regions to decrease device size and improve costs.
1 . An integrated circuit device, including:
a semiconductor substrate providing a first region;
a second region formed over the first region;
an input buffer circuit having an input terminal coupled to receive an input signal, the input buffer including at least one insulated gate field effect transistor (IGFET) formed in the second region, the at least one IGFET including a plurality of substantially horizontally disposed channels that are substantially vertically aligned;
the IGFET having a control gate terminal coupled to a first electrostatic discharge (ESD) protection circuit structure, the ESD protection circuit structure is substantially formed within the first region
wherein the input signal is received from external to the integrated circuit device.
2 . The integrated circuit device of claim 1 , wherein:
the first ESD protection circuit structure includes a first diode formed in the first region, the first diode having an anode terminal electrically connected to a first reference potential and a cathode terminal coupled to the input terminal.
3 . The integrated circuit device of claim 2 , wherein:
the first ESD protection circuit structure includes a second diode formed in the first region, the second diode having a cathode terminal electrically connected to a second reference potential and an anode terminal coupled to the input terminal.
4 . The integrated circuit device of claim 1 , wherein:
the first ESD protection circuit structure includes a semiconductor controlled rectifier (SCR) circuit formed in the first region.
5 . The integrated circuit device of claim 4 , wherein:
the SCR circuit has a first terminal coupled to the control gate of the IGFET and a second terminal electrically connected to a first reference potential.
6 . The integrated circuit device of claim 1 , wherein:
the input buffer circuit includes a p-type IGFET and an n-type IGFET, each IGFET including a plurality of substantially horizontally disposed channels that are substantially vertically aligned;
the p-type IGFET has a drain coupled to a drain of the n-type IGFET; and
the n-type IGFET has a source coupled to a first reference potential and a control gate terminal coupled to the first ESD protection circuit structure.
7 . The integrated circuit device of claim 1 , further includes:
the first ESD protection circuit structure includes a first IGFET formed in the first region, the first IGFET having a source/drain path coupled between the control gate terminal of the at least one IGFET formed over the first insulator layer and a first reference potential and a control gate coupled to the first reference potential.
8 . The integrated circuit device of claim 1 , further including:
the first ESD protection circuit structure further includes a second IGFET formed in the semiconductor substrate, the second IGFET having a source/drain path coupled between the control gate terminal of the at least one IGFET formed over the first insulator layer and a power supply potential and a control gate coupled to the power supply potential.
9 . The integrated circuit device of claim 1 , further including:
the first ESD protection circuit structure includes an ESD protection circuit formed in the first region and a resistor formed in the first region, the ESD protection circuit has a terminal electrically connected to a first terminal of the resistor, the resistor has a second terminal electrically connected to the input terminal of the input buffer.
10 . The integrated circuit device of claim 9 , wherein:
the ESD protection circuit includes a first diode formed in the first region, the first diode having an anode terminal electrically connected to a first reference potential and a cathode terminal electrically connected to the first terminal of the resistor.
11 . The integrated circuit device of claim 10 , wherein:
the ESD protection circuit includes a second diode formed in the first region, the second diode having a cathode terminal electrically connected to a second reference potential and an anode terminal electrically connected to the first terminal of the resistor.
12 . The integrated circuit device of claim 9 , wherein:
the ESD protection circuit includes a semiconductor controlled rectifier (SCR) circuit formed in the first region, the SCR circuit has a first terminal electrically connected to the first terminal of the resistor and a second terminal electrically connected to a first reference potential.
13 . The integrated circuit device of claim 9 , wherein:
the ESD protection circuit includes a first IGFET formed in the first region, the first IGFET having a source/drain path electrically connected between the first terminal of the resistor and a first reference potential and a control gate coupled to the first reference potential.
14 . The integrated circuit device of claim 13 , wherein:
the ESD protection circuit includes further includes a second IGFET formed in the semiconductor substrate, the second IGFET having a source/drain path coupled between the first terminal of the resistor and a power supply potential and a control gate coupled to the power supply potential.
15 . The integrated circuit device of claim 1 , wherein:
the first region includes at least one planar IGFET having a single gate structure.
16 . The integrated circuit device of claim 15 , wherein:
the at least one IGFET including a plurality of substantially horizontally disposed channels that are substantially vertically aligned has a gate length of less than about 6 nm and the at least one planar IGFET has a gate length of at least 10 nm.
17 . The integrated circuit device of claim 1 , wherein:
the first region includes at least FinFET having a single gate structure over a fin shaped semiconductor area.
18 . The integrated circuit device of claim 1 , wherein:
the at least one IGFET including a plurality of substantially horizontally disposed channels that are substantially vertically aligned has a gate length of less than about 6 nm and the at least one FinFET has a gate length of at least 7 nm.
19 . The integrated circuit device of claim 1 , further including:
the input buffer coupled to receive an input enable signal, the input enable signal enables the input buffer when the input enable signal has a first logic level and disables the input buffer when the input enable signal has a second logic level.
20 . The integrated circuit device of claim 19 , wherein:
the input buffer is coupled to receive a reference potential, the reference potential provides a threshold potential for identifying a logic level of the input signal; and
the at least one IGFET formed in the second region includes a control gate structure that substantially surrounds each of the plurality of substantially horizontally disposed channels.