ESD protection for integrated circuit devices
An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include electrostatic discharge (ESD) protection circuit structures. The ESD protection circuit structures may be formed in regions other than the region that the IGFETs are formed as well as in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming ESD protection circuit structures in regions below the IGFETs, an older process technology may be used and device size may be decreased. Furthermore, planar IGFETs of FinFETs may be formed in other regions to decrease device size and improve costs.
1. An integrated circuit device, comprising:
an internal circuit coupled between a first power supply potential and a second power supply potential, the internal circuit having an input terminal coupled to receive an input signal and an output terminal coupled to provide an output signal, the internal circuit including at least one insulated gate field effect transistor (IGFET) including a plurality of substantially horizontally disposed channels that are substantially vertically aligned; and
a first electrostatic discharge (ESD) protection circuit structure electrically connected between the first power supply potential and the second power supply potential
wherein the internal circuit is not electrically connected to receive a signal generated external to the integrated circuit device and is not electrically connected to provide a signal external to the integrated circuit device;
a semiconductor substrate providing a first region;
a second region formed over the first region;
the at least one insulated gate field effect transistor (IGFET) is formed in the second region; and
the first ESD protection circuit structure is substantially formed within the first region.
2. The integrated circuit device of claim 1 , wherein:
the first ESD protection circuit structure includes a diode.
3. The integrated circuit device of claim 2 , wherein:
the diode includes an anode terminal electrically connected to the first power supply potential and a cathode region electrically connected to the second power supply potential.
4. The integrated circuit device of claim 1 , wherein:
the first ESD circuit structure includes a SCR circuit coupled between the first power supply potential and the second power supply potential.
5. The integrated circuit device of claim 1 , wherein:
the internal circuit includes
a p-type IGFET including a plurality of substantially horizontally disposed channels that are substantially vertically aligned and having a control gate that substantially surrounds the substantially horizontally disposed channels; and
an n-type IGFET including a plurality of substantially horizontally disposed channels that are substantially vertically aligned and having a control gate that substantially surrounds the substantially horizontally disposed channels.
6. The integrated circuit device of claim 5 , wherein:
the p-type IGFET and n-type IGFET are configured as an inverter circuit.
7. The integrated circuit device of claim 1 , wherein:
the first and second power supply potentials are received from external to the integrated circuit device.
8. The integrated circuit device of claim 1 , further including:
an input buffer circuit coupled to receive an input signal generated external to the integrated circuit device, the input signal received at a first pad.
9. The integrated circuit device of claim 8 , further including:
a second ESD protection circuit structure having a first terminal electrically connected between the first pad and an input terminal of the input buffer circuit.
10. The integrated circuit device of claim 9 , wherein:
the second ESD protection circuit structure includes a resistor electrically connected between the first terminal of the second ESD protection circuit structure and the input terminal of the input buffer circuit.
11. The integrated circuit device of claim 10 , wherein:
the second ESD protection circuit structure further includes a first diode having an anode terminal coupled to the first terminal of the second ESD protection circuit structure.
12. The integrated circuit device of claim 11 , wherein:
the second ESD protection circuit structure further includes a second diode having a cathode terminal coupled to the first terminal of the second ESD protection circuit structure.
13. The integrated circuit device of claim 11 , wherein:
the first diode including a plurality of substantially horizontally disposed current carrying regions that are substantially vertically aligned.
14. The integrated circuit device of claim 1 , further including:
an output buffer circuit coupled to receive an input signal and provide an output signal externally to the integrated circuit device through a first pad.
15. The integrated circuit device of claim 14 , further including:
a second ESD protection circuit structure having a first terminal electrically connected between the first pad and an output terminal of the output buffer circuit.
16. The integrated circuit device of claim 15 , wherein:
the second ESD protection circuit structure further includes a first diode having an anode terminal coupled to the first terminal of the second ESD protection circuit structure.
17. The integrated circuit device of claim 16 , further including:
the second ESD protection circuit structure further includes a second diode having a cathode terminal coupled to the first terminal of the second ESD protection circuit structure.
18. The integrated circuit device of claim 16 , wherein:
the first diode including a plurality of substantially horizontally disposed current carrying regions that are substantially vertically aligned.
19. An integrated circuit device, comprising:
an internal circuit coupled between a first power supply potential and a second power supply potential, the internal circuit having an input terminal coupled to receive an input signal and an output terminal coupled to provide an output signal, the internal circuit including at least one insulated gate field effect transistor (IGFET) including a plurality of substantially horizontally disposed channels that are substantially vertically aligned; and
a first electrostatic discharge (ESD) protection circuit structure electrically connected between the first power supply potential and the second power supply potential
wherein the internal circuit is not electrically connected to receive a signal generated external to the integrated circuit device and is not electrically connected to provide a signal external to the integrated circuit device wherein
the first ESD protection circuit structure includes a diode, the diode including a plurality of substantially horizontally disposed current carrying regions that are substantially vertically aligned and each substantially horizontally disposed current carrying region forms a p-n junction diode.