Unified memory management for a multiple processor system
Various multi-processor unified memory management systems and methods are detailed herein. In embodiments detailed herein, inter-chip memory management modules may be executed by processors that are in communication via an inter-chip link. A flat memory map may be used across the multiple processors of the system. Each inter-chip memory management module may analyze memory transactions. If the memory transaction is directed to a portion of the flat memory map managed by another processor, the memory-transaction may be translated to a non-memory mapped transaction and transmitted via an inter-chip communication link.
1. A multi-processor unified memory management system, comprising:
a first programmable processor system that communicates via an inter-chip link with a second programmable processor system, wherein the first programmable processor system comprises:
a first inter-chip memory management module configured to:
analyze memory access transactions;
translate outbound memory-mapped transactions into non-memory mapped transactions comprising coded memory address data; and
translate inbound non-memory mapped transactions into memory-mapped transactions based on coded memory address data; and
the second programmable processor system that communicates via the inter-chip link with the first programmable processor system, wherein the second programmable processor system comprises:
a second inter-chip memory management module configured to:
analyze memory access transactions;
translate outbound memory-mapped transactions into non-memory mapped transactions comprising coded memory address data; and
translate inbound non-memory mapped transactions into memory-mapped transactions based on coded memory address data.
2. The multi-processor unified memory management system of claim 1 , wherein the first inter-chip memory management module is further configured to:
analyze a memory access transaction;
determine that the memory access transaction involves a memory address accessible via the second programmable processor system; and
in response to determining that the memory access transaction involves the memory address accessible via the second programmable processor system, output a non-memory mapped transaction via an inter-chip high speed link to the second programmable processor, wherein the non-memory mapped transaction comprises coded memory address data.
3. The multi-processor unified memory management system of claim 2 , wherein the second inter-chip memory management module is further configured to receive the non-memory mapped transaction from the first inter-chip memory management module.
4. The multi-processor unified memory management system of claim 3 , wherein the second inter-chip memory management module is further configured to store data from the received non-memory mapped transaction into memory at a memory location based on the coded memory address data included in the non-memory mapped transaction.
5. The multi-processor unified memory management system of claim 1 , further comprising:
a first memory directly accessible by only the first programmable processor system; and
a second memory directly accessible by only the second programmable processor.
6. The multi-processor unified memory management system of claim 1 , wherein the first inter-chip memory management module and the second inter-chip memory management module use a common flat memory map.
7. The multi-processor unified memory management system of claim 1 , wherein the first programmable processor system comprises a first field programmable gate array (FPGA).
8. The multi-processor unified memory management system of claim 7 , wherein the second programmable processor system comprises a second FPGA.
9. The multi-processor unified memory management system of claim 7 , wherein the second programmable processor system comprises a reduced instruction set computer (RISC) processor.
10. The multi-processor unified memory management system of claim 1 , wherein the first inter-chip memory management module and the second inter-chip memory management module are each configured to process both memory mapped transactions and non-memory mapped transactions in any order in which the transactions are received.
11. A method for using a unified memory management system, the method comprising:
outputting, by a native processing module of a first processor, a memory transaction;
determining, by a first inter-chip memory management module executed by the first processor, that the memory transaction corresponds to a portion of a flat memory map that is managed by another processor;
translating, by the first inter-chip memory management module, the memory transaction into a non-memory mapped memory transaction;
transmitting, by the first inter-chip memory management module, the translated memory transaction via an inter-chip link to a second inter-chip memory management module of a second processor;
translating, by the second inter-chip memory management module, the translated memory transaction into a memory-mapped memory transaction; and
performing, by the second inter-chip memory management module, the memory-mapped memory transaction.
12. The method for using the unified memory management system of claim 11 , wherein the non-memory mapped memory transaction is a stream-based memory transaction.
13. The method for using the unified memory management system of claim 11 , further comprising:
receiving, by the second inter-chip memory management module, the transmitted translated memory transaction via the inter-chip link.
14. The method for using the unified memory management system of claim 13 , further comprising:
determining, by the second inter-chip memory management module, that the transmitted translated memory transaction is not to be forwarded.
15. The method for using the unified memory management system of claim 14 , wherein determining that the transmitted translated memory transaction is not to be forwarded is based on the portion of the flat memory map being managed by the second inter-chip memory management module of the second processor.
16. The method for using the unified memory management system of claim 11 , wherein the first processor is a first field-programmable gate array (FPGA) and the second processor is a second FPGA.
17. The method for using the unified memory management system of claim 11 , wherein performing the memory-mapped memory transaction comprises storing data from the memory transaction into memory at a memory location based on coded memory address data included in the non-memory mapped transaction.
18. The method for using the unified memory management system of claim 17 , wherein a memory address corresponding to the flat memory map is transmitted via a side-band communication as part of transmitting the translated memory transaction via the inter-chip link.
19. The method for using the unified memory management system of claim 11 , wherein transmitting, by the first inter-chip memory management module, the translated memory transaction via the inter-chip link to the second inter-chip memory management module of the second processor comprises:
forwarding, by a third inter-chip memory management module of a third processor, the translated memory transaction via the inter-chip link to the second inter-chip memory management module of the second processor.
20. The method for using the unified memory management system of claim 19 , wherein the first processor is connected with the second processor only via the third processor.