Reference free and temperature independent voltage-to-digital converter
A system and method for measuring power supply variations are described. A functional unit includes one or more power supply monitors capable of measuring power supply variations. The power supply monitors forego use of a clock signal from clock generating circuitry and forego use of a reference voltage from a reference power supply. The power supply monitors use an output of a source ring oscillator as a clock signal for the sequential elements of a counter. The counter measures a number of revolutions of a measuring ring oscillator within a period of the output of the source oscillator. The revolutions of the measuring ring oscillator are associated with a number of rising edges and falling edges of the output signal of the measuring ring oscillator. An encoder converts the output of the sequential elements to a binary value, and sends the binary value to an external age tracking unit.
1. An apparatus comprising:
a first ring oscillator configured to generate a first signal with a first period based on a received power supply;
a second ring oscillator configured to generate a second signal with a second period based on the received power supply;
a counter configured to count a number of cycles of the second signal within the first period of the first signal; and
circuitry configured to convey the count to an external age tracking unit configured to compare the count to an expected count, based at least in part on a determination that the first period has elapsed.
2. The apparatus as recited in claim 1 , wherein the counter is configured to use the first signal as a clock signal input.
3. The apparatus as recited in claim 2 , wherein the circuitry is further configured to convey the count prior to a clock signal being generated by clock generating circuitry.
4. The apparatus as recited in claim 1 , wherein the apparatus further comprises an encoder, wherein:
the counter is further configured to store, in a plurality of sequential elements, a state of one or more stages of the second ring oscillator using the first signal in place of a clock signal input, wherein the state comprises an indication of the number of cycles of the second signal within the first period of the first signal; and
the encoder is configured to convert the state to a binary value indicating the number of cycles of the second signal within the first period of the first signal.
5. The apparatus as recited in claim 1 , wherein the apparatus further comprises a divider configured to:
receive the first signal; and
generate a third signal with a third period N times greater than the first period of the first signal, wherein N is a positive, non-zero integer.
6. The apparatus as recited in claim 5 , wherein the apparatus further comprises circuitry configured to:
select between the first signal and the third signal; and
convey the selected signal to the counter to use as a clock signal input.
7. The apparatus as recited in claim 1 , wherein the first ring oscillator is a one stack ring oscillator and the second ring oscillator is a two stack ring oscillator.
8. A method comprising:
generating, by a first ring oscillator, a first signal with a first period based on a received power supply;
generating, by a second ring oscillator, a second signal with a second period based on the received power supply;
counting, by a counter, a number of cycles of the second signal within the first period of the first signal; and
conveying, by circuitry, the count to an external age tracking unit configured to compare the count to an expected count, based at least in part on a determination that the first period has elapsed.
9. The method as recited in claim 8 , further comprising using, by the counter, the first signal as a clock signal input.
10. The method as recited in claim 8 , further comprising resetting the counter, in response to determining the first period of the first signal has elapsed.
11. The method as recited in claim 8 , further comprising:
storing a state of one or more stages of the second ring oscillator using the first signal in place of a clock signal input, wherein the state comprises an indication of the number of cycles of the second signal within the first period of the first signal; and
converting the state to a binary value indicating the number of cycles of the second signal within the first period of the first signal.
12. The method as recited in claim 8 , further comprising:
receiving, by a divider, the first signal; and
generating, by the divider, a third signal with a third period N times greater than the first period of the first signal, wherein N is a positive, non-zero integer.
13. The method as recited in claim 12 , further comprising:
selecting between the first signal and the third signal; and
conveying the selected signal to the counter to use as a clock signal input.
14. The method as recited in claim 8 , wherein the first ring oscillator is a one stack ring oscillator and the second ring oscillator is a two stack ring oscillator.
15. The method as recited in claim 11 , further comprising:
updating one or more operating parameters, in response to determining a difference between the binary value and an expected value is greater than a threshold; and
maintaining the one or more operating parameters, in response to determining the difference is less than or equal to the threshold.
16. A circuit comprising:
a processor core; and
power supply monitor comprising:
a first ring oscillator configured to generate a first signal with a first period based on a received power supply;
a second ring oscillator configured to generate a second signal with a second period based on the received power supply;
a counter configured to count a number of cycles of the second signal within the first period of the first signal; and
circuitry configured to convey the count to an external age tracking unit configured to compare the count to an expected count, based at least in part on a determination that the first period has elapsed.
17. The circuit as recited in claim 16 , wherein the counter is configured to use the first signal as a clock signal input.
18. The circuit as recited in claim 16 , wherein the circuitry comprises a divider configured to:
receive the first signal; and
generate a third signal with a third period N times greater than the first period of the first signal, wherein N is a positive, non-zero integer.
19. The circuit as recited in claim 18 , wherein the circuitry is further configured to:
select between the first signal and the third signal; and
convey the selected signal to the counter to use as a clock signal input.
20. The circuit as recited in claim 16 , wherein the first ring oscillator is a one stack ring oscillator and the second ring oscillator is a two stack ring oscillator.