Memory structure for self-erasing secret storage
In one embodiment, memory cell includes a control gate, a floating gate, a substrate comprising a source region and a drain region, a first isolator between the control gate and floating gate, and a second isolator between the floating gate and the substrate. The memory cell is configured to have a retention time that is within a statistical window around a selected lifespan. The selected lifespan may be less than ten years, such as, for example, less than one year, less than one month, or less than one week.
1. A system comprising:
a processor coupled to a memory, the memory comprising at least one non-volatile memory cell that is configured to store a charge in a gate and have a retention time that is within a statistical window around a selected lifespan, wherein the gate includes a control gate, and wherein the non-volatile memory cell is stressed by applying cycles of high voltage to the control gate of the non-volatile memory such that the charge is set to leak and continue to leak based on a predetermined amount or percentage over a predetermined amount of time based on the selected lifespan.
2. The system of claim 1 , wherein the selected lifespan is less than ten years, wherein the cycles are applied such that properties of one or more isolators associated with the non-volatile memory cell are reduced to modify thickness of the one or more isolators, or one or more dopants in a channel region are added or removed to modify channel properties associated with a channel between a source and a drain.
3. The system of claim 1 , wherein the statistical window is between 95% of the selected lifespan and 105% of the selected lifespan.
4. The system of claim 1 , wherein the non-volatile memory cell is to store charge based on a control signal being applied thereto and is to leak the stored charge over time based on conductance of an oxide including a leaky gate oxide, and the selected lifespan indicates an amount of time that the stored charge is detectable in the non-volatile memory cell.
5. The system of claim 1 , wherein the memory comprises a flash memory device and the memory cell is integrated in the flash memory device, wherein the gate includes a floating gate, and wherein the non-volatile memory cell includes a floating gate-based memory cell.
6. The system of claim 1 , wherein the system comprises a system-on-chip (SoC).
7. An apparatus comprising:
a non-volatile memory cell including a sidewall storage-based non-volatile memory cell that is configured to have a retention time that is within a statistical window around a selected lifespan, wherein the non-volatile memory cell is configured to store a charge in a gate including a control gate, and wherein the non-volatile memory cell is stressed by applying cycles of high voltage to the control gate of the non-volatile memory such that the charge is set to leak and continue to leak based on a predetermined amount or percentage over a predetermined amount of time based on the selected lifespan.
8. The apparatus of claim 7 , wherein the statistical window is between 95% of the selected lifespan and 105% of the selected lifespan wherein the cycles are applied such that properties of one or more isolators associated with the non-volatile memory cell are reduced to modify thickness of the one or more isolators, or one or more dopants in a channel region are added or removed to modify channel properties associated with a channel between a source and a drain.
9. The apparatus of claim 7 , wherein the memory cell is to store a charge in the control gate based on a control signal being applied to the control gate, is to leak the stored charge over time based on conductance of an oxide including a leaky gate oxide, and the selected lifespan indicates an amount of time that the stored charge is detectable in the sidewall spacer.
10. The apparatus of claim 7 , wherein the apparatus comprises a flash memory device and the memory cell is integrated in the flash memory device, wherein the gate includes a floating gate, and wherein the non-volatile memory cell includes a floating gate-based memory cell.