IP Library Granted Patent US 11,240,895
Granted Patent B2
US 11,240,895 · App. 17/036,947 · Granted Feb 1, 2022

Hybrid driving scheme for RGB color tuning

Inventors: Yifeng Qiu (San Jose, CA); John Grant (Charlotte, NC)
Assignee: Lumileds LLC
H05B45/46H05B45/28H05B45/325H05B45/24H05B45/37H05B45/395
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Quick Facts
Patent No.
US 11,240,895
App. No.
17/036,947
Granted
Feb 1, 2022
Kind
B2
Abstract

A device includes an analog current division circuit configured to divide an input current into a first current and a second current, and a multiplexer array including a plurality of switches to provide the first current to a first of three colors of LEDs and the second current to a second of three colors of LEDs simultaneously during a first portion of a period, the first current to the second of three colors of LEDs and the second current to a third of three colors of LEDs simultaneously during a second portion of the period, and the first current to the first of three colors of LEDs and the second current to the third of three colors of LEDs simultaneously during a third portion of the period.

Claims (73)

1. A circuit comprising:

a current division circuit configured to divide an input current into a first current and a second current; and

a multiplexer array arranged to receive the first current and the second current, the multiplexer array including a plurality of switches arranged to, for each period of a plurality of periods:

provide the first current to a first output and the second current to a second output substantially simultaneously exclusively during a first portion of the period,

provide the first current to the second output and the second current to a third output substantially simultaneously exclusively during a second portion of the period, and

provide the first current to the first output and the second current to the third output substantially simultaneously exclusively during a third portion of the period.

2. The circuit of claim 1 , wherein:

the plurality of switches includes:

a first pair of switches coupled with the first output,

a second pair of switches coupled with the second output, and

a third pair of switches coupled with the third output, and

each of the first pair of switches, the second pair of switches, and the third pair of switches having one switch to which the first current is to be supplied and another switch to which the second current is to be supplied.

3. The circuit of claim 1 , wherein:

the current division circuit is an analog circuit, and

the current division circuit is configured to divide the input current substantially equally during each period such that the first current and the second current are substantially equal.

4. The circuit of claim 1 , wherein:

the current division circuit is an analog circuit, and

the current division circuit is configured to divide the input current unequally during each period such that the first current and the second current are unequal.

5. The circuit of claim 1 , wherein the plurality of switches includes:

a first switch coupled with the first output,

a second switch coupled with the second output, and

a third switch coupled with the third output.

6. The circuit of claim 5 , wherein:

a control terminal of the first switch is provided with a first control input,

a control terminal of the second switch is to be provided with a second control input,

a control terminal of the third switch is to be provided with a third control input, and

the second control input is the inverse of the first control input or the inverse of the third control input.

7. The circuit of claim 5 , wherein the plurality of switches includes a fourth switch coupled with the second output and the third output.

8. The circuit of claim 7 , wherein:

a control terminal of the first switch is to be provided with a first control input,

a control terminal of the second switch is to be provided with a second control input, the second control input is the inverse of the first control input,

a control terminal of the third switch is to be provided with a third control input, and

a control terminal of the fourth switch is to be provided with a fourth control input, the third control input is the inverse of the fourth control input.

9. A circuit board comprising:

a temperature sensor arranged to determine a temperature of the circuit board;

a multiplexer array arranged to receive a first current and a second current, the multiplexer array including a plurality of switches arranged to, for each period of a plurality of periods:

provide the first current to a first output and the second current to a second output substantially simultaneously exclusively during a first portion of the period,

provide the first current to the second output and the second current to a third output substantially simultaneously exclusively during a second portion of the period, and

provide the first current to the first output and the second current to the third output substantially simultaneously exclusively during a third portion of the period; and

a microcontroller configured to receive an indication of the temperature of the circuit board from the temperature sensor and compensate for changes caused by changes in the temperature of the circuit board.

10. The circuit board of claim 9 , further comprising:

a first load coupled with the first output, a second load coupled with the second output, and a third load coupled with the third output; and

a current driver coupled with a voltage regulator that together are configured to produce a stabilized current that is to be supplied to the first load, the second load, and the third load.

11. The circuit board of claim 9 , further comprising an analog current division circuit configured to divide an input current into the first current and the second current substantially equally during each period such that the first current and the second current are substantially equal.

12. The circuit board of claim 9 , further comprising an analog current division circuit configured to divide an input current into the first current and the second current unequally during each period such that the first current and the second current are unequal.

13. The circuit board of claim 9 , wherein the plurality of switches includes:

a first switch coupled with the first output,

a second switch coupled with the second output, and

a third switch coupled with the third output.

14. The circuit board of claim 13 , wherein:

a control terminal of the first switch is to be provided with a first control input,

a control terminal of the second switch is to be provided with a second control input,

a control terminal of the third switch is to be provided with a third control input, and

the second control input is the inverse of the first control input or the inverse of the third control input.

15. The circuit board of claim 13 , wherein the plurality of switches includes a fourth switch coupled with the second output and the third output.

16. The circuit board of claim 15 , wherein:

a control terminal of the first switch is to be provided with a first control input,

a control terminal of the second switch is to be provided with a second control input, the second control input is the inverse of the first control input,

a control terminal of the third switch is to be provided with a third control input, and

a control terminal of the fourth switch is to be provided with a fourth control input, the third control input is the inverse of the fourth control input.

17. The circuit board of claim 10 , wherein the first load is a first light emitting diode (LED) array configured to emit light of a first color, the second load is a second LED array configured to emit light of a second color, and the third load is a third LED array configured to emit light of a third color.

18. The circuit board of claim 10 , further comprising an analog current division circuit configured to divide an input current into the first current and the second current, the microcontroller further configured to monitor an absolute value of the input current and compensate for changes caused by changes in the stabilized current.

19. A method for providing currents to a plurality of loads on a circuit board, the method comprising:

dividing an input current on the circuit board into a first current and a second current;

for each period of a plurality of periods:

providing, to a first load, the first current to a first output and the second current to a second output substantially simultaneously exclusively during a first portion of the period,

providing, to a second load, the first current to the second output and the second current to a third output substantially simultaneously exclusively during a second portion of the period, and

providing, to a third load, the first current to the first output and the second current to the third output substantially simultaneously exclusively during a third portion of the period;

monitoring a temperature of the circuit board; and

adjusting the input current for changes caused by changes in the temperature of the circuit board.

20. The method of claim 19 , further comprising:

producing a stabilized current that is supplied to the first load, the second load, and the third load; and

monitoring an absolute value of the input current and compensating for changes caused by changes in the stabilized current.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2025
From: LUMILEDS LLC
To: LUMILEDS SINGAPORE PTE. LTD.
Reel/Frame 071888/0086 →
RELEASE OF SECURITY INTEREST Recorded Jan 29, 2025
From: SOUND POINT AGENCY LLC
To: LUMILEDS LLC; LUMILEDS HOLDING B.V.
Reel/Frame 070046/0001 →
SECURITY INTEREST Recorded Jan 5, 2023
From: LUMILEDS LLC; LUMILEDS HOLDING B.V.
To: SOUND POINT AGENCY LLC
Reel/Frame 062299/0338 →
PATENT SECURITY AGREEMENT Recorded Dec 9, 2022
From: LUMILEDS, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 062114/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2021
From: LUMILEDS HOLDING B.V.
To: LUMILEDS LLC
Reel/Frame 055047/0159 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 4, 2020
From: QIU, YIFENG; GRANT, JOHN
To: LUMILEDS HOLDING B.V.
Reel/Frame 054271/0255 →