Battery pack and charging control method therefor
A battery pack includes: a charging voltage detector for detecting charging voltage applied to a charging path; a charging first transistor disposed in series on the charging path for controlling charging current flowing through the charging path; a charging second transistor for controlling operation of the charging first transistor; and a controller for controlling operation of the charging first transistor and the charging second transistor. Based on the charging current detected by a charging current detector and the charging voltage detected by the charging voltage detector, the controller can adjust the charging current for charging the battery block, by controlling second ON resistance that is ON resistance of the charging second transistor in a linear region of the charging second transistor, and by controlling first ON resistance that is ON resistance of the charging first transistor in a linear region of the charging first transistor using the second ON resistance.
1. A battery pack comprising:
a battery block formed by connecting a plurality of secondary battery cells in series or in parallel to each other;
a charging path that the battery block is charged;
a charging current detector that detects charging current flowing through the charging path;
a charging voltage detector that detects charging voltage applied to the charging path;
a charging first transistor disposed in series on the charging path, the charging first transistor controlling the charging current flowing through the charging path;
a charging second transistor that controls operation of the charging first transistor; and
a controller that controls operation of the charging first transistor and the charging second transistor,
wherein the charging voltage detector detects the charging voltage applied downstream of the charging first transistor and upstream of the battery block in the charging path, and
wherein based on the charging current detected by the charging current detector and the charging voltage detected downstream of the charging first transistor and upstream of the battery block by the charging voltage detector, the controller adjusts the charging current for charging the battery block, by controlling second ON resistance that is ON resistance of the charging second transistor in a linear region of the charging second transistor, and by controlling first ON resistance that is ON resistance of the charging first transistor in a linear region of the charging first transistor using the second ON resistance.
2. The battery pack according to claim 1 , further comprising a low-pass circuit connected to a gate side of the charging second transistor.
3. The battery pack according to claim 1 , further comprising:
a resistor connected in parallel between a source and a drain of the charging second transistor; and
a charging third transistor connected in series with the resistor,
wherein the controller controls the charging third transistor to be ON during charging so as to electrically connect the resistor in parallel between the source and the drain of the charging second transistor, thereby relaxing an amount of change in the ON resistance of the charging second transistor.
4. The battery pack according to claim 1 , wherein the controller performs constant power control on the charging first transistor and controls to adjust the charging current of the battery block.
5. The battery pack according to claim 1 , further comprising a charging semiconductor element disposed on the charging path in series with the charging first transistor, the charging semiconductor element controlling the charging current flowing through the charging path.
6. The battery pack according to claim 1 , wherein the charging first transistor or the charging second transistor comprises an FET.
7. A charging control method for a battery pack that includes
a battery block formed by connecting a plurality of secondary battery cells in series and/or in parallel to each other,
a charging path where the battery block is charged,
a charging current detector that detects charging current flowing through the charging path,
a charging voltage detector that detects charging voltage applied to the charging path,
a charging first transistor disposed in series on the charging path, the charging first transistor controlling the charging current flowing through the charging path,
a charging second transistor that controls operation of the charging first transistor, and
a controller that controls operation of the charging first transistor and the charging second transistor,
the charging control method for the battery pack, comprising:
detecting charging current for charging the battery block by the charging current detector, and detecting charging voltage for charging the battery block by the charging voltage detector, said charging voltage being detected downstream of the charging first transistor and upstream of the battery block in the charging path; and
adjusting the charging current for charging the battery block by the controller based on the detected charging current and the detected charging voltage detected downstream of the charging first transistor and upstream of the battery block, by controlling second ON resistance that is ON resistance of the charging second transistor in a linear region of the charging second transistor, and by controlling first ON resistance that is ON resistance of the charging first transistor in a linear region of the charging first transistor using the second ON resistance.
8. The charging control method according to claim 7 , wherein the battery pack further comprises:
a resistor connected in parallel between a source and a drain of the charging second transistor; and
a charging third transistor connected in series with the resistor,
wherein the controller controls the charging third transistor to be ON during charging so as to electrically connect the resistor in parallel between the source and the drain of the charging second transistor, thereby relaxing an amount of change in the ON resistance of the charging second transistor.