Granted Patent B2

US 12,339,979 · App. 17/060,355 · Granted Jun 24, 2025

Inventor: Ion-Alexandru Ionescu (Seattle, WA)

Assignee: CrowdStrike, Inc.

G06F21/6218G06F3/0622G06F3/0655G06F3/0679G06F9/45558G06F21/54G06F21/554G06F21/566G06F2009/45583G06F2009/45587G06F21/53G06F2221/034

Abstract

Claims (56)

1. A computer-implemented method comprising:

storing memory addresses of control registers of an operating system of the computing device in debug registers or model specific registers (MSRs) of the computing device, the memory addresses including a memory address not permitted by the operating system to be stored in the debug registers or MSRs;

determining control registers to be protected;

setting intercepts for the memory addresses stored in the debug registers or MSRs;

monitoring a read operation from malware attempting to read one of the memory addresses stored in a corresponding one of the debug registers or MSRs;

in response to monitoring the read operation from the malware attempting to read the one of the memory addresses:

returning deceptive data to the malware that provides a false indication of success to the malware, and

performing a security action including killing the read operation from the malware;

monitoring a write operation attempting to write an off value to one of the control registers to be protected, the off value turning off a security feature that prevents a processor of the operating system from performing write operations on the control registers; and

in response to monitoring the write operation attempting to write the off value to the one of the control registers to be protected:

allowing the write operation to write the off value to an alternate memory location different from the memory addresses of the control registers, and

returning a false indication that the security feature has been set to the off value.

2. The computer-implemented method of claim 1 , further comprising setting privilege attributes for memory pages which include the memory addresses.

3. The computer-implemented method of claim 2 , further comprising identifying other memory locations to be intercepted and setting privilege attributes for memory pages that include the other memory locations.

4. The computer-implemented method of claim 1 , wherein setting the intercepts for the memory addresses stored in the debug registers or MSRs comprises setting intercepts for instructions seeking to read the debug registers or MSRs.

5. The computer-implemented method of claim 1 , wherein the memory address not permitted by the operating system to be stored in the debug registers or MSRs is associated with a kernel-mode component.

6. The computer-implemented method of claim 1 , wherein in response to monitoring the write operation attempting to write the off value to the one of the control registers further comprises at least one of: killing the write operation, or remembering that the process sought to write the off value.

7. The computer-implemented method of claim 6 , wherein the one of the control registers includes an on setting for a security feature of the operating system.

8. The computer-implemented method of claim 1 , wherein the computer-implemented method is performed by a security agent on the computing device.

9. The computer-implemented method of claim 8 , wherein the security agent initiates a security agent component as a hypervisor for the computing device.

10. The computer-implemented method of claim 1 , further comprising:

monitoring a read operation from the operating system attempting to read one of the debug registers or MSRs; and

in response to monitoring the read operation from the operating system, returning an operating-system-permitted value corresponding to a memory address permitted by the operating system for the one of the debug registers or MSRs to the operating system.

11. A non-transitory computer-readable medium having stored thereon executable instructions which, when executed by a computing device, cause the computing device to perform operations comprising:

storing memory addresses of control registers of an operating system of the computing device in debug registers or model specific registers (MSRs) of the computing device, the memory addresses including a memory address not permitted by the operating system to be stored in the debug registers or MSRs;

determining control registers to be protected;

setting intercepts for the memory addresses stored in the debug registers or MSRs;

monitoring a read operation from malware attempting to read one of the memory addresses stored in a corresponding one of the debug registers or MSRs;

in response to monitoring the read operation from the malware attempting to read the one of the memory addresses:

returning deceptive data to the malware that provides a false indication of success to the malware, and

performing a security action including killing the read operation from the malware;

monitoring a write operation attempting to write an off value to one of the control registers to be protected, the off value turning off a security feature that prevents a processor of the operating system from performing write operations on the control registers;

in response to monitoring the write operation attempting to write the off value to the one of the control registers to be protected:

allowing the write operation to write the off value to an alternate memory location different from the memory addresses of the control registers, and

returning a false indication that the security feature has been set to the off value.

12. The non-transitory computer-readable medium of claim 11 , wherein the operations further comprise setting privilege attributes for memory pages which include the memory addresses.

13. The non-transitory computer-readable medium of claim 12 , wherein the operations further comprise identifying other memory locations to be intercepted and setting privilege attributes for memory pages that include the other memory locations.

14. The non-transitory computer-readable medium of claim 11 , wherein setting the intercepts for the debug registers or MSRs comprises setting intercepts for instructions seeking to read the debug registers or MSRs.

15. The non-transitory computer-readable medium of claim 11 , wherein the memory address not permitted by the operating system to be stored in the debug registers or MSRs is associated with a kernel-mode component.

16. The non-transitory computer-readable medium of claim 11 , wherein the operations further comprise:

monitoring a read operation from the operating system attempting to read one of the debug registers or MSRs; and in response to monitoring the read operation from the operating system, returning an operating-system-permitted value corresponding to a memory address permitted by the operating system for the one of the debug registers or MSRs to the operating system.

17. A computing device comprising:

a processor; and

memory coupled to the processor, the memory storing thereon executable instructions which, when executed by processor, cause the processor to perform operations, the operations comprising:

storing memory addresses of control registers of an operating system of the computing device in debug registers or model specific registers (MSRs) of the computing device, the memory addresses including a memory address not permitted by the operating system to be stored in the debug registers or MSRs;

determining control registers to be protected;

setting intercepts for the memory addresses stored in the debug registers or MSRs;

monitoring a read operation from malware attempting to read one of the memory addresses stored in a corresponding one of the debug registers or MSRs;

in response to monitoring the read operation from the malware attempting to read the one of the memory addresses:

returning deceptive data to the malware that provides a false indication of success to the malware, and

performing a security action including killing the read operation from the malware;

monitoring a write operation attempting to write an off value to one of the control registers to be protected, the off value turning off a security feature that prevents a processor of the operating system from performing write operations on the control registers;

in response to monitoring the write operation attempting to write the off value to the one of the control registers to be protected:

allowing the write operation to write the off value to an alternate memory location different from the memory addresses of the control registers, and

returning a false indication that the security feature has been set to the off value.

18. The computing device of claim 17 , wherein the operations are performed by a security agent on the computing device, and the security agent initiates a security agent component as a hypervisor for the computing device.

Assignments (3)

Continuity (2)

References Cited (400)