IP Library Granted Patent US 11,102,878
Granted Patent B1
US 11,102,878 · App. 17/061,483 · Granted Aug 24, 2021

High-speed trace breakout methods and systems

Inventor: Umesh Chandra (Santa Cruz, CA)
Assignee: DELL PRODUCTS L.P.
H05K1/0228H05K1/116H05K2201/09509
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Quick Facts
Patent No.
US 11,102,878
App. No.
17/061,483
Granted
Aug 24, 2021
Kind
B1
Abstract

A high-speed transmission circuit design reduces or eliminates the presence of unwanted stub-effects and avoids uncontrolled line impedances that in existing circuits cause impedance mismatches that give rise to unwanted reflections and, ultimately, degrade signal integrity, e.g., in belly-to-belly configurations involving Quad Small Form-Factor Pluggable Double Density (QSFP DD) connectors. In various embodiments, by preventing overcrowding of signal lines, the circuit design further reduces crosstalk and increases signal integrity.

Claims (30)

1. A high-speed transmission circuit comprising:

a first set of connector pin legs that are positioned in a direction towards an edge of a printed circuit board (PCB), the first set of connector pin legs when being disposed on a first surface of the PCB use a first via to couple the first surface to a first signal path within the PCB, the first signal path breaking out in the direction towards the edge of the PCB; and

a second set of connector pin legs that are positioned in a direction away from the edge of the PCB, the second set of connector pin legs, when being disposed on a second surface that is opposite to the first surface of the PCB, use a second via to couple the second surface to a second signal path within the PCB, the second signal path breaking out in the direction away from the edge of the PCB.

2. The high-speed transmission circuit of claim 1 , further comprising a signal via that couples the first surface with the first signal path.

3. The high-speed transmission circuit of claim 2 , wherein the signal via is a blind via.

4. The high-speed transmission circuit of claim 1 , wherein the first signal path is arranged in a stripline configuration, the first signal path being at least partially formed between a first ground path and a second ground path.

5. The high-speed transmission circuit of claim 4 , wherein the first ground path is located adjacent to the first surface.

6. The high-speed transmission circuit of claim 4 , wherein the first ground path and at least a portion of the first surface form a microstrip.

7. The high-speed transmission circuit of claim 4 , further comprising a ground via that couples the first surface is coupled to the first ground path, first signal path, and second ground path to reduce unwanted signal emissions.

8. The high-speed transmission circuit of claim 7 , wherein the ground via is a plated through hole that extends from the first surface to the second surface.

9. The high-speed transmission circuit of claim 7 , wherein a portion of the ground via that extends from the first surface to the first signal path serves as a return path for a signal via that couples the first surface with the first signal path.

10. A printed circuit board (PCB) for high-speed signals, the PCB comprising:

a first surface;

a first conductive pad disposed on the first surface to receive a first connector pin that serves as part of a first signal path for a high-speed signal, the first conductive pad comprising a first pad region that is not considered part of the first signal path, the first connector pin comprising a first connector pin leg that is positioned in a direction towards an edge of the PCB;

a first via that couples the first surface to a first layer within the PCB, the first layer routes the first signal path in the direction towards the edge of the PCB;

a second surface that is opposite to the first surface of the PCB;

a second conductive pad disposed on the second surface to receive a second connector pin that serves as part of a second signal path, the second connector pin comprising a second connector pin leg that is positioned in a direction away from the edge of the PCB; and

a second via that couples the second surface to a second layer within the PCB, the second layer routes the second signal path in the direction away from the edge of the PCB.

11. The PCB of claim 10 , further comprising a blind via that couples the first surface with the first signal path.

12. The PCB of claim 10 , wherein the first signal path is arranged in a stripline configuration, the first signal path being at least partially formed between a first ground path and a second ground path.

13. The PCB of claim 12 , further comprising a ground via that couples the first surface is coupled to the first ground path, first signal path, and second ground path to reduce unwanted signal emissions.

14. The PCB of claim 13 , wherein a portion of the ground via that extends from the first surface to the first layer serves as a return path for a signal via that couples the first surface with the first signal path.

15. A method for reducing or eliminating unwanted resonant stub effects while controlling impedance of a high-speed signal breakout on a printed circuit board (PCB), the method comprising:

applying a first voltage to a first signal path that comprises a first connector pin having a first connector pin leg, the first connector pin leg being disposed on a first surface of the PCB, being positioned in a direction towards an edge of the PCB, and using a first via to couple the first surface to the first signal path that breaks out in the direction towards the edge of the PCB; and

applying a second voltage to a second signal path that comprises a second connector pin having a second connector pin leg, the second connector pin leg being disposed on a second surface of the PCB, being positioned in a direction away from an edge of the PCB, and using a second via to couple the second surface to the second signal path that breaks out in the direction away from the edge of the PCB.

16. The method of claim 15 , further comprising a blind via that couples the first surface with the first signal path.

17. The method of claim 15 , wherein the first signal path is arranged in a stripline configuration, the first signal path being at least partially formed between a first ground path and a second ground path.

18. The method of claim 17 , further comprising a ground via that couples the first surface is coupled to the first ground path, first signal path, and second ground path to reduce unwanted signal emissions.

19. The method of claim 18 , wherein a portion of the ground via that extends from the first surface to a second layer serves as a return path for a signal via that couples the first surface with the first signal path.

20. The method of claim 18 , wherein the first ground path and at least a portion of the first surface form a microstrip.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (054475/0523) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: EMC IP HOLDING COMPANY LLC; DELL PRODUCTS L.P.
Reel/Frame 060332/0664 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (054475/0434) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: EMC IP HOLDING COMPANY LLC; DELL PRODUCTS L.P.
Reel/Frame 060332/0740 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (054475/0609) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: EMC IP HOLDING COMPANY LLC; DELL PRODUCTS L.P.
Reel/Frame 062021/0570 →
RELEASE OF SECURITY INTEREST AT REEL 054591 FRAME 0471 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058001/0463 →
SECURITY INTEREST Recorded Nov 18, 2020
From: EMC IP HOLDING COMPANY LLC; DELL PRODUCTS L.P.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 054475/0609 →
SECURITY INTEREST Recorded Nov 18, 2020
From: EMC IP HOLDING COMPANY LLC; DELL PRODUCTS L.P.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 054475/0434 →
SECURITY INTEREST Recorded Nov 18, 2020
From: EMC IP HOLDING COMPANY LLC; DELL PRODUCTS L.P.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 054475/0523 →
SECURITY AGREEMENT Recorded Nov 13, 2020
From: EMC IP HOLDING COMPANY LLC; DELL PRODUCTS L.P.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 054591/0471 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 3, 2020
From: CHANDRA, UMESH
To: DELL PRODUCTS L.P.
Reel/Frame 053967/0680 →