Pipeline using match-action blocks

1. An apparatus comprising:

an output bus;

a match table configured to store a plurality of entries, each entry of the plurality of entries including a key value, wherein the match table specifies a matching entry in response to being queried by query data received from the output bus, wherein the query data comprises state data and key data;

one or more storage devices configured to store operation information for each of the plurality of entries stored in the match table, wherein the operation information specifies one or more instructions associated with each respective entry in the plurality of entries stored in the match table; and

logic connected to the output bus, the match table, and the one or more storage devices, wherein the logic is configured to:

receive one or more operands from the output bus;

identify one or more instructions in the one or more storage devices; and

generate, based on the one or more instructions and the one or more operands, processed data, and

wherein the logic is further configured to:

receive the state data and the key data;

determine, based on the one or more instructions and the one or more operands, new state data;

determine, based on the one or more instructions and the one or more operands, a new key value; and

output new query data comprising an indication of the new state data and the new key value.

2. The apparatus of claim 1 , wherein the one or more instructions are one or more first instructions for a first action block, wherein the one or more operands are one or more first operands for the first action block, wherein the processed data is first processed data, and wherein the logic is further configured to:

identify one or more second instructions for a second action block in the one or more storage devices;

receive one or more second operands for the second action block from the output bus; and

generate, based on the first processed data, the one or more second instructions and the one or more second operands, second processed data.

3. The apparatus of claim 1 ,

wherein the one or more operands comprises one or more single bit flags; or

wherein the one or more operands comprises one or more nibbles.

4. The apparatus of claim 1 , wherein the logic comprises a Very Long Instruction Word (VLIW) action processor configured to execute a plurality of VLIW instructions in parallel and using the one or more operands.

5. The apparatus of claim 4 ,

wherein the VLIW action processor is configured to execute the VLIW instruction with a fixed number of micro-operations; and

wherein each micro-operation of the fixed number of micro-operations is configured to conditionally update contents of the output bus.

6. The apparatus of claim 1 ,

wherein the match table comprises a ternary content-addressable memory (TCAM) and wherein at least a portion of the key value is configured to be masked in response to the TCAM being queried by the query data;

wherein the match table comprises Hashtable; or

wherein the match table comprises a direct index.

7. The apparatus of claim 1 ,

wherein the one or more storage devices comprises an action instruction memory (AIM);

wherein an entry of the match table comprises an Action Identifier (AID) specifying an index into a respective entry of the AIM; and

wherein, to identify the one or more instructions in the one or more storage devices, the logic is configured to identify the respective entry of the AIM.

8. The apparatus of claim 1 ,

wherein the one or more storage devices comprises an array of function arguments;

wherein an entry of the match table comprises an action argument pointer specifying an index into a respective entry of the array of function arguments; and

wherein, to identify the one or more instructions from the one or more storage devices, the logic is configured to identify the respective entry of the array of function arguments.

9. The apparatus of claim 1 , wherein the output bus comprises a packet buffer configured to store information about incoming packets, and wherein, to generate the processed data, the logic is further configured to:

parse a network packet header stored within the packet buffer, wherein the network packet headers include at least one of an Ethernet packet header, a VLAN packet header, and an IP version 4 packet header.

10. The apparatus of claim 9 , wherein, to generate the processed data, the logic is further configured to:

extract the query data from the packet buffer.

11. An apparatus comprising:

an output bus, wherein the output bus comprises a packet buffer configured to store information about incoming packets and a parsed result vector;

a match table configured to store a plurality of entries, each entry of the plurality of entries including a key value, wherein the match table specifies a matching entry in response to being queried by query data received from the output bus;

one or more storage devices configured to store operation information for each of the plurality of entries stored in the match table, wherein the operation information specifies one or more instructions associated with each respective entry in the plurality of entries stored in the match table; and

logic connected to the output bus, the match table, and the one or more storage devices, wherein the logic is configured to:

receive one or more operands from the output bus;

identify one or more instructions in the one or more storage devices;

generate, based on the one or more instructions and the one or more operands, processed data, wherein, to generate the processed data, the logic is further configured to parse a network packet header stored within the packet buffer, wherein the network packet headers include at least one of an Ethernet packet header, a VLAN packet header, and an IP version 4 packet header; and

write data to the parsed result vector.

12. The apparatus of claim 1 , wherein, to determine the new key value, the logic is further configured to:

access data from the output bus.

13. The apparatus of claim 1 , wherein the logic is further configured to:

determine an initial value for the state data;

determine an initial value for the key data;

initialize the match table with match table entry data;

initialize the one or more storage devices with initial storage device values;

identify an end state; and

determine if the state data matches the end state.

14. A method comprising:

generating, by a match table, an index for operation information specifying one or more operations for a matching entry stored in the match table in response to being queried by query data, wherein the query data comprises state data and key data;

identifying, by logic implemented in circuitry and based on the index, one or more instructions in one or more storage devices;

receiving, by the logic, one or more operands from the output bus;

generating, by the logic, processed data based on the one or more instructions and the one or more operands;

receiving, by the logic, the state data and the key data;

determining, by the logic and based on the one or more instructions and the one or more operands, new state data;

determining, by the logic and based on the one or more instructions and the one or more operands, a new key value; and

outputting, by the logic, new query data comprising an indication of the new state data and the new key value.

15. The method of claim 14 , wherein the one or more instructions are one or more first instructions for a first action block, wherein the one or more operands are one or more first operands for the first action block, and wherein the processed data is first processed data, the method further comprising:

identifying, by the logic, one or more second instructions for a second action block in the one or more storage devices;

receiving, by the logic, one or more second operands for the second action block from the output bus; and

generating, by the logic, based on the first processed data, the one or more second instructions and the one or more second operands, second processed data.

16. The method of claim 14 ,

wherein the one or more operands comprises one or more single bit flags; or

wherein the one or more operands comprises one or more nibbles.

17. The method of claim 1 , wherein the logic comprises a Very Long Instruction Word (VLIW) action processor configured to execute a plurality of VLIW instructions in parallel and using the one or more operands.

18. The method of claim 17 ,

wherein the VLIW action processor is configured to execute the VLIW instruction with a fixed number of micro-operations; and

wherein each micro-operation of the fixed number of micro-operations is configured to conditionally update contents of the output bus.

19. The method of claim 14 , wherein determining the new key value comprises accessing data from the output bus.

20. The method of claim 14 , further comprising:

determining, by the logic, an initial value for the state data;

determining, by the logic, an initial value for the key data;

initializing, by the logic, the match table with match table entry data;

initializing, by the logic, the one or more storage devices with initial storage device values;

identifying, by the logic, an end state; and

determining, by the logic, if the state data matches the end state.