Forward error correction systems and methods
Techniques for performing forward error correction of data to be transmitted over an optical communications channel. The techniques include: receiving data bits; organizing the data bits into an arrangement having a plurality of blocks organized into rows and columns and into a plurality of strands including a first strand of blocks that includes a back portion comprising a first row of the plurality of blocks, and a front portion comprising blocks from at least two different columns in at least two different rows other than the first row of blocks; and encoding at least some of the data bits in the arrangement using a first error correcting code at least in part by generating first parity bits by applying the first error correcting code to first data bits in the front portion of the first strands and second data bits in the back portion of the first strand.
1. An apparatus for performing forward error correction of data to be transmitted over an optical communications channel, the apparatus comprising:
an input interface;
a preprocessor comprising circuitry coupled to the input interface and configured to:
organize data bits received from the input interface into an arrangement having a plurality of blocks organized into rows and columns, the plurality of blocks further organized into a plurality of strands of blocks including a first strand of blocks, the first strand of blocks comprising:
a back portion comprising a first row of the plurality of blocks, and
a front portion comprising blocks from at least two different columns in at least two different rows other than the first row of blocks; and
an encoder comprising circuitry configured to encode at least some of the data bits in the arrangement using a first error correcting code at least in part by:
accessing first data bits in the front portion of the first strand of blocks;
accessing second data bits in the back portion of the first strand of blocks; and
generating first parity bits by applying the first error correcting code to the first data bits and the second data bits; wherein each of the plurality of blocks is an m by m block, wherein accessing the first data bits comprises accessing Tm data bits in the front portion of the first strand of blocks, wherein accessing the second data bits comprises accessing Tm−p data bits in the back portion of the first strand of blocks, wherein p is a positive integer, and wherein generating the first parity bits comprises generating p parity bits using the Tm data bits accessed in the front portion of the first strand of blocks and Tm−p data bits accessed in the back portion of the first strand of blocks.
2. The apparatus of claim 1 , wherein the plurality of blocks is organized into a plurality of epochs, each of the plurality of epochs comprising S rows and T columns of blocks, wherein S and T are positive integers, wherein the back portion of the first strand is in epoch e, wherein e is a positive integer, and
wherein accessing the first data bits in the front portion of the first strand comprises accessing a column of data from each block in a set of T blocks associated with a set of labels given by:
{( e−Δ− 1,κ(1),λ( s )),( e−Δ− 2,κ(2),λ( s )), . . . ,( e−Δ−T ,κ( T ),λ( s ))},
wherein Δ is a non-negative integer,
wherein λ( ) is a permutation of the integers 1, . . . , S, and
wherein κ( ) is a permutation of the integers 1, . . . , T.
3. The apparatus of claim 2 , wherein accessing the second data bits in the back portion of the first strand comprises accessing data from at least some of the blocks in a set of T blocks associated with a set of labels given by: {(e,1,s), (e,2,s), . . . , (e,T,s)}.
4. The apparatus of claim 1 , wherein applying the first error correcting code to the first data bits and the second data bits is performed by using a binary parity check matrix associated with the first error correcting code.
5. The apparatus of claim 4 , wherein applying the first error correcting code to the first data bits and the second data bits is performed by using a first permuted binary parity check matrix generated by permuting rows of the binary parity check matrix using a first permutation.
6. The apparatus of claim 5 , wherein the plurality of strands includes a second strand, and wherein the encoder is configured to generate second parity bits using data bits in the second strand at least in part by using a second permuted binary parity check matrix generated by permuting rows of the binary parity check matrix using a second permutation different from the first permutation.
7. The apparatus of claim 1 , further comprising a memory configured to store the arrangement.
8. The apparatus of claim 1 , wherein each block in the plurality of blocks is in a front portion of one strand in the plurality of strands and is also in a back portion of another strand in the plurality of strands.
9. The apparatus of claim 8 , wherein each block in the plurality of blocks is part of exactly two strands in the plurality of strands.
10. An apparatus for performing forward error correction of data to be transmitted over an optical communications channel, the apparatus comprising:
an input interface configured to receive the data to be transmitted over the optical communications channel;
a memory configured to store an arrangement of data bits, the arrangement having a plurality of blocks organized into rows and columns, the plurality of blocks further organized into a plurality of strands of blocks including a first strand of blocks, the first strand of blocks comprising:
a back portion comprising a first row of the plurality of blocks, and
a front portion comprising blocks from at least two different columns in at least two different rows other than the first row of blocks; and
an encoder comprising circuitry coupled to the input interface and configured to:
access first data bits in the front portion of the first strand of blocks;
obtain second data bits via the input interface;
encode the first data bits and the second data bits at least in part by generating first parity bits by applying a first error correcting code to the first data bits and the second data bits; and
store the second data bits and the generated first parity in the back portion of the first strand; wherein the first error correcting code is a cyclic error correcting code or a shortened cyclic error correcting code.
11. The apparatus of claim 10 , wherein applying the first error correcting code to the first data bits and the second data bits is performed by using a binary parity check matrix associated with the first error correcting code.
12. The apparatus of claim 11 , wherein applying the first error correcting code to the first data bits and the second data bits is performed by using a first permuted binary parity check matrix generated by permuting rows of the binary parity check matrix using a first permutation.
13. The apparatus of claim 12 , wherein the plurality of strands includes a second strand, and wherein the encoder is configured to generate second parity bits using data bits in the second strand at least in part by using a second permuted binary parity check matrix generated by permuting rows of the binary parity check matrix using a second permutation different from the first permutation.
14. The apparatus of claim 10 , wherein the first error correcting code is a Bose, Chaudhuri, and Hocquenghem (BCH) code or a shortened BCH code.
15. The apparatus of claim 10 , further configured to transmit the first data bits, the second data bits, and the first parity bits over the optical communications channel.
16. The apparatus of claim 10 , wherein each block in the plurality of blocks is in a front portion of one strand in the plurality of strands and is also in a back portion of another strand in the plurality of strands.
17. The apparatus of claim 16 , wherein each block in the plurality of blocks is part of exactly two strands in the plurality of strands.