Method and structure for controlling bandwidth and peaking over gain in a variable gain amplifier (VGA)
A method of controlling bandwidth and peaking over gain in a variable gain amplifier (VGA) device and structure therefor. The device includes at least three differential transistor pairs configured as a cross-coupled differential amplifier with differential input nodes, differential bias nodes, differential output nodes, a current source node, and two cross-coupling nodes. The cross-coupled differential amplifier includes a load resistor coupled to each of the differential output nodes and one of the cross-coupling nodes, and a load inductor coupled to the each of the cross-coupling nodes and a power supply rail. A current source is electrically coupled to the current source node. The cross-coupling configuration with the load resistance and inductance results in a lower bandwidth and lowered peaking at low gain compared to high gain. Further, the tap point into the inductor can be chosen as another variable to “tune” the bandwidth and peaking in a communication system.
1. A variable gain amplifier (VGA) device comprising:
a first differential transistor pair having a first differential input, a first coupled node, and a first differential output;
a second differential transistor pair having a second differential input, a second coupled node, and a second differential output; and
a third differential transistor pair having a third differential input, a third coupled node, and a third differential output; the third differential input being configured as a VGA differential input receiving a differential input signal, the third coupled node being coupled to a grounded current source
wherein first outputs of the first and second differential outputs are coupled to a power supply rail through respective load resistors and load inductors; and
wherein the load inductors include tunable tap points to tune at least one of bandwidth and peaking.
2. The device of claim 1 wherein each of the differential transistor pairs is a pair of bipolar junction transistors (BJTs).
3. The device of claim 1 wherein each of the differential transistor pairs is a pair of field effect transistors (FETs).
4. The device of claim 1 wherein the load resistors comprise a first load resistor and a second load resistor, wherein the load inductors comprise a first load inductor and a second load inductor, and wherein the first output of the first differential output is coupled to the first load resistor, the first load resistor being coupled to the first load inductor, and the first load inductor being coupled to the power supply rail; and the first output of the second differential output is coupled to the second load resistor, the second load resistor being coupled to the second load inductor, the second load inductor being coupled to the power supply rail; and
wherein a second output of the first differential output is coupled to a node between the second load resistor and the second load inductor, and wherein a second output of the second differential output is coupled to a node between the first load resistor and the first load inductor;
the device further comprising a first isolation resistor coupled between the second output of the first differential output and the node between the second load resistor and the second load inductor; and a second isolation resistor coupled between the second output of the second differential output and the node between the first load resistor and the first load inductor.
5. The device of claim 4 wherein the tunable tap points comprise a first tunable tap point and a second tunable tap point; wherein the first load inductor includes the first tunable tap point; wherein the second load inductor includes the second tunable tap point; and wherein the first and second tunable tap points are configured to reduce the peaking at low gain.
6. The device of claim 1 wherein the differential input signal is a differential radio frequency (RF) input signal;
wherein a first input of the first differential input and a first input of the second differential input are configured to receive a first bias signal of a VGA differential bias signal;
wherein a second input of the first differential input and a second input of the second differential input are configured to receive a second bias signal of the VGA differential bias signal; and
wherein the VGA differential bias signal is a differential local oscillator (LO) signal or a static differential gain control signal.
7. The device of claim 1 further comprising a first degeneration resistor and a second degeneration resistor configured symmetrically within the third differential transistor pair around the third coupled node; and wherein a first output of the third differential output is coupled to the first coupled node and a second output of the third differential output is coupled to the second coupled node.
8. The device of claim 1 wherein a first output of the first differential output and a first output of the second differential output are configured as a VGA differential output; and wherein the VGA differential output is characterized by the following: v 0 =[Rα+sL(2α−1)]i s , where v o is an output voltage on the first or second load resistor, R is a value of the first or second load resistor, α is a current steering factor, L is a value of the first or second load inductor, i s is a signal current generated from an input signal Y ip −V in , and R+sL represents a load configuration.
9. A variable gain amplifier (VGA) device comprising:
a cross-coupled differential amplifier configured as a Gilbert cell having first and second transistors, differential input nodes, differential bias nodes, differential output nodes, a current source node, and two cross-coupling nodes; wherein the cross-coupled differential amplifier receives a differential input signal at the differential input nodes, and the first and second transistors receives a differential bias signal at the differential bias nodes;
wherein the cross-coupled differential amplifier includes first and second load resistors each coupled to each of the differential output nodes and one of the cross-coupling nodes;
wherein the cross-coupled differential amplifier includes first and second load inductors each coupled to the each of the cross-coupling nodes and a power supply rail; and
a current source electrically coupled to the current source node;
wherein the first load inductor includes a first tunable tap point and wherein the second load inductor includes a second tunable tap point; and
wherein the first and second tunable tap points are configured to reduce peaking at low gain.
10. The device of claim 9 wherein each of the first and second transistors is a bipolar junction transistor (BJT), and wherein each of the differential bias nodes is a base node.
11. The device of claim 9 wherein each of the first and second transistors is a field effect transistor (FET), and wherein each of the differential bias nodes is a gate node.
12. A variable gain amplifier (VGA) device comprising:
a cross-coupled differential amplifier configured as a Gilbert cell having first and second transistors, differential input nodes, differential bias nodes, differential output nodes, a current source node, and two cross-coupling nodes; wherein the cross-coupled differential amplifier receives a differential input signal at the differential input nodes, and the first and second transistors receives a differential bias signal at the differential bias nodes;
wherein the cross-coupled differential amplifier includes first and second load resistors each coupled to each of the differential output nodes and one of the cross-coupling nodes;
wherein the cross-coupled differential amplifier includes first and second load inductors each coupled to the each of the cross-coupling nodes and a power supply rail; and
a current source electrically coupled to the current source node;
the device further comprising:
a first isolation resistor electrically coupled between the first transistor and a first one of the cross-coupling nodes; and
a second isolation resistor electrically coupled between the second transistor and a second one of the cross-coupling nodes.
13. The device of claim 9 further comprising:
third and fourth transistors receiving the different input signal at the differential input nodes;
a first degeneration resistor electrically coupled between the third transistor and the current source node; and
a second degeneration resistor electrically coupled between the fourth transistor and the current source node.
14. The device of claim 9 wherein the differential input signal is a differential radio frequency (RF) input signal; and wherein the differential bias signal is a differential local oscillator (LO) signal or a static differential gain control signal.
15. The device of claim 9 wherein the differential output nodes are characterized by the following: v 0 =[Rα+sL(2α−1)]i s , where v o is an output voltage on the first or second load resistor, R is a value of the first or second load resistor, α is a current steering factor, L is a value of the first or second load inductor, i s is a current from the current source, and R+sL represents a load configuration.
16. The device of claim 1 wherein a second output of the first differential output is coupled to a node between the second load resistor and the second load inductor, and wherein a second output of the second differential output is coupled to a node between the first load resistor and the first load inductor;
the device further comprising a first isolation resistor coupled between the second output of the first differential output and the node between the second load resistor and the second load inductor; and a second isolation resistor coupled between the second output of the second differential output and the node between the first load resistor and the first load inductor.
17. The device of claim 9 further comprising:
a first isolation resistor electrically coupled between the first transistor and a first one of the two cross-coupling nodes; and
a second isolation resistor electrically coupled between the second transistor and a second one of the two cross-coupling nodes.
18. The device of claim 12 further comprising:
third and fourth transistors receiving the different input signal at the differential input nodes;
a first degeneration resistor electrically coupled between the third transistor and the current source node; and
a second degeneration resistor electrically coupled between the fourth transistor and the current source node.
19. The device of claim 12 wherein:
the first load inductor includes a first tunable tap point and wherein the second load inductor includes a second tunable tap point; and
the first and second tunable tap points are configured to reduce peaking at low gain.
20. The device of claim 12 wherein the differential output nodes are characterized by the following: v 0 =[Rα+sL(2α−1)]i s , where v o is an output voltage on the first or second load resistor, R is a value of the first or second load resistor, α is a current steering factor, L is a value of the first or second load inductor, i s is a current from the current source, and R+sL represents a load configuration.