IP Library Granted Patent US 11,307,242
Granted Patent B1
US 11,307,242 · App. 17/066,187 · Granted Apr 19, 2022

Quantum error-correction in microwave integrated quantum circuits

Inventors: William J. Zeng (Berkeley, CA); Eyob A. Sete (Walnut Creek, CA); Chad Tyler Rigetti (Walnut Creek, CA)
Assignee: Rigetti & Co, LLC
G01R31/2851G06N10/00
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Quick Facts
Patent No.
US 11,307,242
App. No.
17/066,187
Granted
Apr 19, 2022
Kind
B1
Abstract

In a general aspect, a quantum error-correction technique includes applying a first set of two-qubit gates to qubits in a lattice cell, and applying a second, different set of two-qubit gates to the qubits in the lattice cell. The qubits in the lattice cell include data qubits and ancilla qubits, and the ancilla qubits reside between respective nearest-neighbor pairs of the data qubits. After the first and second sets of two-qubit gates have been applied, measurement outcomes of the ancilla qubits are obtained, and the parity of the measurement outcomes is determined.

Claims (33)

1. A quantum computing system comprising:

a quantum processor cell comprising a device lattice;

a control system communicably coupled to the quantum processor cell to control the device lattice, the control system configured to:

apply a first set of two-qubit gates to qubits in a lattice cell in the device lattice, the qubits in the lattice cell comprising data qubits and ancilla qubits, the ancilla qubits in the lattice cell residing between respective nearest-neighbor pairs of the data qubits in the lattice cell;

apply a second, different set of two-qubit gates to the qubits in the lattice cell; and

after applying the first and second sets of two-qubit gates, obtaining measurement outcomes of the ancilla qubits in the lattice cell; and

determine a parity of the measurement outcomes;

wherein the quantum processor cell includes one or more of fluxonium devices and transmon devices.

2. The quantum computing system of claim 1 , wherein applying a first set of two-qubit gates comprises applying a first set of controlled-not gates, and applying a second set of two-qubit gates comprises a second, different set of controlled-not gates.

3. The quantum computing system of claim 2 , wherein at least one of the controlled-not gates is applied to qubits defined respectively by a fluxonium device and a transmon device, and applying the controlled-not gate comprises tuning an operating frequency of the fluxonium device to an operating frequency of the transmon device.

4. The quantum computing system of claim 2 , wherein at least one of the controlled-not gates is applied to qubits defined respectively a fluxonium device and a transmon device, and applying the controlled-not gate comprises tuning an operating frequency of the fluxonium device to the |1 →|2 transition frequency of the transmon device.

5. The quantum computing system of claim 1 , wherein the lattice cell comprises:

transmon devices that define the data qubits; and

fluxonium devices that define the ancilla qubits.

6. The quantum computing system of claim 1 , wherein the lattice cell comprises:

fluxonium devices that define the data qubits; and

transmon devices that define the ancilla qubits.

7. The quantum computing system of claim 1 , wherein the lattice cell comprises:

a first group of fluxonium devices that define the data qubits; and

a second group of fluxonium devices that define the ancilla qubits.

8. The quantum computing system of claim 1 , wherein the lattice cell comprises:

a first group of transmon devices that define the data qubits; and

a second group of transmon devices that define the ancilla qubits.

9. A quantum computing system comprising:

a quantum processor cell comprising a device lattice;

a control system communicably coupled to the quantum processor cell to control the device lattice, the control system configured to:

apply a first set of two-qubit gates to qubits in a lattice cell in the device lattice, the qubits in the lattice cell comprising data qubits and ancilla qubits, the ancilla qubits in the lattice cell residing between respective nearest-neighbor pairs of the data qubits in the lattice cell;

apply a second, different set of two-qubit gates to the qubits in the lattice cell; and

after applying the first and second sets of two-qubit gates, obtaining measurement outcomes of the ancilla qubits in the lattice cell; and

determine a parity of the measurement outcomes;

wherein a rectilinear lattice comprises the lattice cell.

10. The quantum computing system of claim 9 , wherein the parity is used for quantum error-correction in a surface code applied to the rectilinear lattice.

11. The quantum computing system of claim 9 , wherein the parity is used for quantum error-correction in a color code applied to the rectilinear lattice.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Dec 12, 2024
From: TRINITY CAPITAL INC.
To: RIGETTI & CO, LLC
Reel/Frame 069603/0771 →
RELEASE OF SECURITY INTEREST Recorded Dec 12, 2024
From: TRINITY CAPITAL INC.
To: RIGETTI & CO, LLC; RIGETTI INTERMEDIATE LLC; RIGETTI COMPUTING, INC.
Reel/Frame 069603/0831 →
AMENDED AND RESTATED INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Jul 8, 2024
From: RIGETTI & CO, LLC; RIGETTI INTERMEDIATE LLC; RIGETTI COMPUTING, INC.
To: TRINITY CAPITAL INC.
Reel/Frame 068146/0416 →
CHANGE OF NAME Recorded Mar 9, 2022
From: RIGETTI & CO, INC.
To: RIGETTI & CO, LLC
Reel/Frame 059356/0909 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2020
From: ZENG, WILLIAM J.; SETE, EYOB A.; RIGETTI, CHAD T.
To: RIGETTI & CO, INC.
Reel/Frame 054012/0720 →
Cited By (2)
US 12,321,219 US 12,510,586