IP Library Granted Patent US 11,493,812
Granted Patent B2
US 11,493,812 · App. 17/066,493 · Granted Nov 8, 2022

Display device and semiconductor device

Inventors: Isao Suzumura (Tokyo, JP); Fumiya Kimura (Tokyo, JP); Kazuhide Mochizuki (Tokyo, JP); Hitoshi Tanaka (Tokyo, JP); Kenichi Akutsu (Tokyo, JP); Atsuko Shimada (Tokyo, JP)
Assignee: JAPAN DISPLAY INC.
G02F1/136227G02F1/1368G02F1/136286G02F1/13685G02F1/134318G02F1/134363G02F1/136295G02F2201/123G02F2201/40H01L27/1225
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Quick Facts
Patent No.
US 11,493,812
App. No.
17/066,493
Granted
Nov 8, 2022
Kind
B2
Abstract

According to one embodiment, a display device includes a semiconductor layer, a first insulating layer, a gate electrode, a second insulating layer and a plurality of transparent conductive layers. The transparent conductive layers include a pixel electrode, a first conductive layer and a second conductive layer. The pixel electrode is in contact with the second conductive layer. The second conductive layer is in contact with the first conductive layer. The first conductive layer is brought into contact with a second region of the semiconductor layer through a first contact hole.

Claims (30)

1. A display device comprising:

a semiconductor layer including a first region, a second region and a channel region between the first region and the second region;

a first insulating layer located on the semiconductor layer;

a gate electrode located on the first insulating layer and opposing the channel region;

a second insulating layer located on the first insulating layer and the gate electrode; and

a pixel electrode located above the second insulating layer and electrically connected to the second region;

a plurality of gates lines extending in the first direction and arranged in the second direction, with intervals therebetween;

a plurality of source lines extending in the second direction and arranged in the first direction with intervals therebetween, to intersect the plurality of gates lines;

a first transparent conductive layer provided on the second insulating layer and brought into contact with the second region through a first contact hole formed in the first insulating layer and the second insulating layer;

a third insulating layer located on the second insulating layer and the first transparent conductive layer; and

a second transparent conductive layer provided on the third insulating layer and brought into contact with the first transparent conductive layer through a second contact hole formed in the third insulating layer,

the channel region being bent in a region overlapping the gate electrode,

the channel region including a first portion extending in a first direction and a second portion extending in a second direction intersecting the first direction,

the second direction being not parallel to the first direction,

the first portion and the second portion overlapping the gate electrode,

the gate electrode being electrically connected to one of the plurality of gate lines and being located in a region where a respective one of the plurality of gate lines and a respective one of the plurality of source lines overlap,

the channel region being bent in a region where a respective one of the plurality of gate lines and a respective one of the plurality of source lines overlap each other,

the first transparent conductive layer being located in an open area surrounded by a respective adjacent pair of gate lines of the plurality of gate lines and a respective adjacent pair of source lines of the plurality of source lines,

the pixel electrode being electrically connected to the second region via the first transparent conductive layer and the second transparent conductive layer,

the third insulating layer including a colored layer comprising a first flat surface on a side opposing the second transparent conductive layer, and an organic insulating layer located between the colored layer and the second transparent conductive layer and comprising a second flat surface brought into contact with the second transparent conductive layer,

in a direction parallel to the second flat surface, a second minimum distance from a central axis of the second contact hole to the second flat surface being less than a first minimum distance from the central axis of the second contact hole to the first flat surface.

2. The device of claim 1 , wherein

the second region is located in the open area together with the first transparent conductive layer, and

the semiconductor layer is formed of an oxide semiconductor.

3. The device of claim 1 , further comprising:

a first substrate;

a second substrate disposed to oppose the first substrate with a gap therebetween; and

a liquid crystal layer held between the first substrate and the second substrate,

wherein

the first substrate includes the semiconductor layer, the first insulating layer, the gate electrode, the second insulating layer and the pixel electrode.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 9, 2020
From: SUZUMURA, ISAO; KIMURA, FUMIYA; MOCHIZUKI, KAZUHIDE; TANAKA, HITOSHI; AKUTSU, KENICHI; SHIMADA, ATSUKO
To: JAPAN DISPLAY INC.
Reel/Frame 054014/0889 →
Priority Claims (1)
JP JP2019-187855 · Oct 11, 2019 · national
Continuity (1)
Related Publication 20210109412A1 · Apr 15, 2021