Integrated circuit structures with well boundary distal to substrate midpoint and methods to form the same
The disclosure provides integrated circuit (IC) structures and methods to form the same. Methods according to the disclosure may be performed on a substrate having a first doping type, the substrate extending between a first end and a second end. A deep well is formed within the substrate, the deep well including a well boundary defined between the deep well and a remainder of the substrate. The well boundary is horizontally distal to a midpoint between the first end and the second end of the substrate. A first active semiconductor region is formed at least partially over the substrate, and an oppositely-doped second active semiconductor region is formed at least partially over the deep well.
1. A method of forming an integrated circuit (IC) structure, the method comprising:
forming a deep well within a substrate, the substrate having a first doping type and the deep well having a second doping type opposite the first doping type, wherein the deep well extends between a first end and a second end and includes a well boundary defined between the deep well and a remainder of the substrate, the well boundary being horizontally distal to a midpoint between the first end and the second end of the substrate;
forming a first active semiconductor region of the second doping type at least partially over the substrate;
forming a second active semiconductor region of the first doping type at least partially over the deep well, wherein the second active semiconductor region is horizontally distal to the well boundary;
forming a gate structure over the first active semiconductor region and the second active semiconductor region;
forming a power rail adjacent a first end of the gate structure; and
forming a grounding rail adjacent a second end of the gate structure, opposite the power rail.
2. The method of claim 1 , further comprising:
forming a set of source/drain (S/D) contacts within the first active semiconductor region or the second active semiconductor region.
3. The method of claim 2 , further comprising forming an insulator film on the substrate, wherein the first active semiconductor region and the second active semiconductor region each define portions of a fully depleted semiconductor on insulator (FDSOI) region.
4. The method of claim 2 , further comprising forming a plurality of logic cells over the substrate and the deep well, wherein each of the plurality of logic cells includes the deep well with the well boundary horizontally distal to the midpoint between the first end and the second end of the substrate.
5. The method of claim 2 , further comprising:
measuring a leakage current across the set of S/D contacts; and
for subsequent deep well formation, modifying a mask used to form the deep well to change a location of the well boundary based on the measured leakage current.
6. The method of claim 1 , wherein the first doping type is N-type doping, the second doping type is P-type doping, and forming the first active semiconductor region and the second active semiconductor region includes doping the first active semiconductor region and the second active semiconductor region to have distinct doping concentrations with respect to the deep well.
7. The method of claim 1 , wherein the well boundary is vertically aligned with a bottom surface of the first active semiconductor region.
8. An integrated circuit (IC) structure comprising:
a substrate having a first doping type;
a deep well within the substrate, the deep well having a second doping type opposite the first doping type, wherein an interface between the substrate and the deep well defines a well boundary within the substrate;
a first active semiconductor region over the substrate and the deep well, the first active semiconductor region having the second doping type, wherein the first active semiconductor region includes a first end over the substrate and a second end over the deep well such that the well boundary is vertically aligned with a bottom surface of the first active semiconductor region;
a second active semiconductor region over the deep well, the second active semiconductor region having the first doping type, wherein the second active semiconductor region is horizontally distal to the well boundary;
a gate structure over the first active semiconductor region and the second active semiconductor region;
a power rail adjacent a first end of the gate structure; and
a grounding rail adjacent a second end of the gate structure.
9. The IC structure of claim 8 , further comprising an insulator film vertically between the substrate and each of the first active semiconductor region and the second active semiconductor region, wherein the first active semiconductor region and the second active semiconductor region each define portions of a fully depleted semiconductor on insulator (FDSOI) region.
10. The IC structure of claim 8 , wherein the first active semiconductor region, the second active semiconductor region, the gate structure, the power rail, and the grounding rail each comprise portions of a logic cell.
11. The IC structure of claim 10 , further comprising a body contact adjacent to the logic cell, wherein the body contact is configured to electrically bias the substrate or the deep well.
12. The IC structure of claim 8 , wherein the first doping type is N-type doping, the second doping type is P-type doping, and wherein a dopant concentration of the first active semiconductor region and the second active semiconductor region is greater than a dopant concentration of the deep well.
13. An integrated circuit (IC) structure comprising:
a substrate having a first doping type;
a deep well within the substrate, having a second doping type opposite the first doping type, wherein an interface between the substrate and the deep well defines a well boundary within the substrate;
a first active semiconductor region over the substrate, the first active semiconductor region having the second doping type, wherein the first active semiconductor region is horizontally distal to the well boundary; and
a second active semiconductor region over the substrate and the deep well, the second active semiconductor region having the first doping type, wherein the second active semiconductor region includes a first end over the substrate and a second end over the deep well, such that the well boundary is vertically aligned with a bottom surface of the second active semiconductor region.
14. The IC structure of claim 13 , further comprising:
a gate structure over the first active semiconductor region and the second active semiconductor region;
a power rail adjacent a first end of the gate structure; and
a grounding rail adjacent a second end of the gate structure.
15. The IC structure of claim 14 , further comprising an insulator film vertically between the substrate and each of the first active semiconductor region and the second active semiconductor region, wherein the first active semiconductor region and the second active semiconductor region each define portions of a fully depleted semiconductor on insulator (FDSOI) region.
16. The IC structure of claim 14 , wherein the first active semiconductor region, the second active semiconductor region, the gate structure, the power rail, and the grounding rail each comprise portions of a logic cell.
17. The IC structure of claim 16 , further comprising a body contact adjacent to the logic cell, wherein the body contact is configured to electrically bias the substrate or the deep well.
18. The IC structure of claim 13 , wherein the first doping type is N-type doping, the second doping type is P-type doping, and wherein a dopant concentration of the first active semiconductor region and the second active semiconductor region is greater than a dopant concentration of the deep well.