IP Library Granted Patent US 11,469,149
Granted Patent B2
US 11,469,149 · App. 17/067,277 · Granted Oct 11, 2022

Semiconductor device and method of forming mold degating structure for pre-molded substrate

Inventors: Henry Descalzo Bathan (Simi Valley, CA); Zigmund Ramirez Camacho (Colorado Springs, CO)
Assignee: Semtech Corporation
H01L23/3121H01L21/565H01L23/13H01L25/0655
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Quick Facts
Patent No.
US 11,469,149
App. No.
17/067,277
Granted
Oct 11, 2022
Kind
B2
Abstract

A semiconductor device has a substrate panel with a substrate having a first substrate area and a second substrate area outside a footprint of the first substrate area. A plurality of semiconductor die or discrete IPDs is disposed over the first substrate area. Substrate area 102 a has electrical interconnect for the semiconductor die. A molding compound is disposed over the semiconductor die and first substrate area using a transfer mold process, which leaves mold culls and mold gates disposed over the second substrate area. A substrate edge is formed in the second substrate area under the mold gates. The substrate edge extends into the first substrate area under the molding compound to reinforce the mold gates and reduce cracking during mold degating. The substrate edge can have a variety of forms such as parallel bars, diagonal bars, orthogonal bars, and combinations thereof.

Claims (31)

1. A semiconductor device, comprising:

a substrate panel including a substrate comprising a first substrate area and a second substrate area outside a footprint of the first substrate area, and a plurality of semiconductor die disposed over the first substrate area;

a molding compound disposed over the plurality of semiconductor die and first substrate area; and

a substrate edge formed in part in the second substrate area and extending from the second substrate area into the first substrate area under the molding compound.

2. The semiconductor device of claim 1 , wherein the substrate edge has a shape selected from a group consisting of solid square, interconnected bars, diagonal bars, and parallel bars.

3. The semiconductor device of claim 1 , wherein a portion of the molding compound extends over the second substrate area.

4. The semiconductor device of claim 1 , wherein the substrate edge includes a cantilever portion extending under the molding compound.

5. The semiconductor device of claim 1 , wherein a surface of the substrate edge is coplanar with a surface of the substrate.

6. The semiconductor device of claim 1 , further including a dummy metal pattern formed on the second substrate area.

7. The semiconductor device of claim 1 , further including a mold gate extending over the second substrate area, wherein the mold gate is supported by the substrate edge.

8. A semiconductor device, comprising:

a substrate panel including a substrate comprising a first substrate area and a second substrate area, and a plurality of semiconductor die disposed over the first substrate area;

a molding compound disposed over the plurality of semiconductor die and first substrate area; and

a substrate edge formed in part in the second substrate area and extending from the second substrate area into the first substrate area.

9. The semiconductor device of claim 8 , wherein the second substrate area is disposed outside a footprint of the first substrate area.

10. The semiconductor device of claim 8 , wherein the substrate edge has a shape selected from a group consisting of solid square, interconnected bars, diagonal bars, and parallel bars.

11. The semiconductor device of claim 8 , wherein a portion of the molding compound extends over the second substrate area.

12. The semiconductor device of claim 8 , wherein the substrate edge includes a cantilever portion extending under the molding compound.

13. The semiconductor device of claim 8 , wherein a surface of the substrate edge is coplanar with a surface of the substrate.

14. The semiconductor device of claim 8 , further including a dummy metal pattern formed on the second substrate area.

15. The semiconductor device of claim 8 , further including a mold gate extending over the second substrate area, wherein the mold gate is supported by the substrate edge.

16. A method of making a semiconductor device, comprising:

providing a substrate panel including a substrate comprising a first substrate area and a second substrate area, and a plurality of semiconductor die disposed over the first substrate area;

depositing a molding compound over the plurality of semiconductor die and first substrate area; and

forming a substrate edge in part in the second substrate area and extending from the second substrate area into the first substrate area.

17. The method of claim 16 , wherein the second substrate area is disposed outside a footprint of the first substrate area.

18. The semiconductor device of claim 16 , wherein the substrate edge has a shape selected from a group consisting of solid square, interconnected bars, diagonal bars, and parallel bars.

19. The semiconductor device of claim 16 , wherein a portion of the molding compound extends over the second substrate area.

20. The semiconductor device of claim 16 , wherein the substrate edge includes a cantilever portion extending under the molding compound.

21. The semiconductor device of claim 16 , wherein a surface of the substrate edge is coplanar with a surface of the substrate.

22. The semiconductor device of claim 16 , further including a dummy metal pattern formed on the second substrate area.

Assignments (2)
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Jan 12, 2023
From: SEMTECH CORPORATION; TRIUNE SYSTEMS, L.L.C.; TRIUNE IP, LLC
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 062389/0057 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 9, 2020
From: BATHAN, HENRY DESCALZO; CAMACHO, ZIGMUND RAMIREZ
To: SEMTECH CORPORATION
Reel/Frame 054020/0799 →