Structure and methods of forming the structure
View Patent ↗Capacitors, apparatus including a capacitor, and methods for forming a capacitor are provided. One such capacitor may include a first conductor a second conductor above the first conductor, and a dielectric between the first conductor and the second conductor. The dielectric does not cover a portion of the first conductor; and the second conductor does not cover the portion of the first conductor not covered by the dielectric.
1. A method of forming a memory structure, comprising:
forming a three-dimensional (3D) memory cell region; and
forming a peripheral region adjacent to the memory cell region, including forming a capacitor structure including multiple conductive levels separated by dielectric levels, comprising:
forming a first conductive level, a second conductive level above the first conductive level, and a third conductive level above the second conductive level;
wherein the second conductive level is stepped back from an upper surface end portion of the first conductive level, and wherein the third conductive level is stepped back from an upper surface end portion of the second conductive level;
wherein the first and second conductive levels are separated by a first dielectric level, and wherein the second and third conductive levels are separated by a second dielectric level.
2. The method of claim 1 , wherein the capacitor structure forms part of a charge pump.
3. The method of claim 1 , wherein forming the 3D memory cell region comprises:
forming multiple vertically offset word lines, each word line separated from at least one vertically adjacent word line level by a dielectric level;
wherein the materials of the first, second, and third conductive levels of the capacitor structure in the peripheral region are formed simultaneously with forming the material of the three vertically offset word lines.
4. The method of claim 3 , wherein the material of the first, second, and third conductive levels of the capacitor structure are the same as the material of the three of the vertically offset word lines.
5. The method of claim 1 , wherein each of the second and third conductive levels of the capacitor are stepped back relative to the same end of the first conductive level, forming a stairstep.
6. The method of claim 1 , wherein each of the second and third conductive levels of the capacitor have a length shorter than the underlying conductive level, and wherein the second and third conductive levels are placed to form stairsteps at both ends of the capacitor structure.
7. The method of claim 1 , further comprising forming a third dielectric level over the third conductive level, and forming a fourth conductive level above the third conductive level, wherein the third conductive level is stepped back from an upper surface end portion of the third conductive level.
8. The method of claim 1 , further comprising multiple vertical contacts extending to a respective conductive level of the first, second, and third conductive levels.
9. The method of claim 1 , wherein forming the 3D memory cell region comprises forming a stacked body comprising N planar conductive levels alternating with N−1 dielectric levels.
10. The method of claim 1 , wherein forming the capacitor structure comprises forming additional conductive levels separated by respective dielectric levels.