IP Library Granted Patent US 11,514,223
Granted Patent B2
US 11,514,223 · App. 17/068,388 · Granted Nov 29, 2022

Systems and methods to extract qubit parameters

Inventors: Reza Molavi (Vancouver, CA); Mark H. Volkmann (Burnaby, CA); Paul I. Bunyk (New Westminster, CA)
Assignee: D-WAVE SYSTEMS INC.
G06F30/398G06F30/392G06N10/00G06F2115/12
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,514,223
App. No.
17/068,388
Granted
Nov 29, 2022
Kind
B2
Abstract

Systems and methods are described to accurately extract device parameters and optimize the design of macroscopic superconducting structures, for example qubits. This method presents the advantage of reusing existing plaquettes to simulate different processor topologies. The physical elements of a qubits are extracted via plurality of plaquettes. Each plaquette contains at least one physical element of the qubit design and has two ports on each side. Each plaquette is concatenated to at least one other plaquette via two ports. The values of inductance (L), capacitance (C) and mutual inductance (M) and quantum critical point of the qubit design can be computed. Changing the physical elements of the qubit design and iterating the method allows to effortlessly refine the qubit design.

Claims (44)

1. A method of operation in a digital processor to extract parameters and optimize a design of a macroscopic superconducting structure, the macroscopic superconducting structure design comprising a plurality of physical elements, the method executed by a digital processor, the method comprising:

forming a plurality of plaquettes, each plaquette representing at least one physical element of a qubit design and having at least two ports, each plaquette concatenated to at least one other plaquette via the at least two ports;

obtaining a representation of the qubit design from the plurality of plaquettes;

extracting a value of inductance (L), a value of capacitance (C) of the qubit design and a value of a mutual inductance M between at least one physical element communicatively coupled to the qubit design and the qubit design;

computing one or more energy scales of the qubit design from a quantum modeling environment via the extracted values of L, C and M;

computing a quantum critical point and

determining whether the quantum critical point is greater than a minimum threshold value.

2. The method of claim 1 wherein forming a plurality of plaquettes includes forming the plurality of plaquettes via an electromagnetic simulator; and obtaining a representation of the qubit design from the plurality of plaquettes via a circuit simulator.

3. The method of claim 1 wherein forming a plurality of plaquettes, each plaquette representing at least one physical element of a qubit design, includes forming the plurality of plaquettes, each plaquette representing at least one physical element of a qubit design selected from a group of physical elements consisting of: compound-compound Josephson junctions, Ip-compensators, inductance tuners, flux bias, readout elements, external coupling devices and internal coupling devices.

4. The method of claim 1 wherein computing one or more energy scales of the qubit design includes computing one or more expected qubit Hamiltonian waveforms as a function of annealing flux.

5. The method of claim 1 wherein computing a quantum critical point includes calculating an intersection between a driver Hamiltonian and a problem Hamiltonian.

6. The method of claim 1 wherein extracting a value of a mutual inductance M between at least one physical element communicatively coupled to the qubit design and the qubit design includes extracting the value of a mutual inductance M between at least one coupling device communicatively coupled to the qubit design and the qubit design.

7. The method of claim 1 further comprising:

in response to determining that the quantum critical point is smaller than a minimum threshold value, iteratively changing a design of at least one of the physical elements of the qubit design to obtain a revised qubit design;

forming a revised plurality of plaquettes, the revised plurality of plaquettes comprising at least one revised plaquette, representing the at least one changed physical element design of the revised qubit design, each plaquette having at least two ports, each plaquette concatenated to another plaquette via the at least two ports;

obtaining a revised representation of the revised the qubit design from the revised plurality of plaquettes;

extracting a value of inductance (L), a value of capacitance (C) of the revised qubit design and a value of a mutual inductance M between at least one physical element communicatively coupled to the revised qubit design and the revised qubit design;

computing one or more energy scales of the revised qubit design from a quantum modeling environment via the extracted values of L, C and M;

computing a quantum critical point of the revised qubit design; and

determining whether the quantum critical point is greater than a minimum threshold value.

8. The method of claim 7 wherein changing a design of at least one of the physical elements of the qubit design to obtain a revised qubit design includes adding additional L-tuners, removing L-tuners, changing the design of coupling devices, and changing a magnitude of an induction coil between the qubit and a first element of a readout.

9. A system comprising:

at least one digital processor; and

at least one non-transitory processor-readable medium communicatively coupleable to the at least one digital processor and that stores at least one processor-executable instruction or data which, when executed by the at least one digital processor, causes the at least one digital processor to:

form a plurality of plaquettes, each plaquette representing at least one physical element of a qubit design, the qubit design comprising a plurality of physical elements, each plaquette having at least two ports, and each plaquette concatenated to at least one other plaquette via the at least two ports;

obtain a representation of the qubit design from the plurality of plaquettes;

extract a value of inductance (L), a value of capacitance (C) of the qubit design and a value of a mutual inductance M between at least one physical element communicatively coupled to the qubit design and the qubit design using the plurality of plaquettes;

compute one or more energy scales of the qubit design from a quantum modeling environment via the extracted values of L, C and M;

compute a quantum critical point; and

determine whether the quantum critical point is greater than a minimum threshold value.

10. The system of claim 9 wherein the at least one non-transitory processor-readable medium communicatively coupleable to the at least one digital processor and that stores at least one processor-executable instruction or data which, when executed by the at least one digital processor, causes the at least one digital processor to: form the plurality of plaquettes via an electromagnetic simulator; and obtain a representation of the qubit design from the plurality of plaquettes via a circuit simulator.

11. The system of claim 9 wherein the at least one non-transitory processor-readable medium communicatively coupleable to the at least one digital processor and that stores at least one processor-executable instruction or data which, when executed by the at least one digital processor, causes the at least one digital processor to form the plurality of plaquettes, each plaquette containing at least one physical element of a qubit design selected from a group consisting of: compound-compound Josephson junctions, Ip-compensators, inductance tuners, flux bias, readout elements, external couplers and internal couplers.

12. The system of claim 9 wherein the at least one non-transitory processor-readable medium communicatively coupleable to the at least one digital processor and that stores at least one processor-executable instruction or data which, when executed by the at least one digital processor, causes the at least one digital processor to compute one or more energy scales of the qubit design by computing one or more expected qubit Hamiltonian waveforms as a function of annealing flux.

13. The system of claim 9 wherein the at least one non-transitory processor-readable medium communicatively coupleable to the at least one digital processor and that stores at least one processor-executable instruction or data which, when executed by the at least one digital processor, causes the at least one digital processor to compute the quantum critical point by calculating an intersection between a driver Hamiltonian and a problem Hamiltonian.

14. The system of claim 9 the at least one non-transitory processor-readable medium communicatively coupleable to the at least one digital processor and that stores at least one processor-executable instruction or data which, when executed by the at least one digital processor, causes the at least one digital processor to extract the value of a mutual inductance M between at least one coupling device communicatively coupled to the qubit design and the qubit design.

15. The system of claim 9 wherein the at least one non-transitory processor-readable medium communicatively coupleable to the at least one digital processor and that stores at least one processor-executable instruction or data which, when executed by the at least one digital processor, further causes the at least one digital processor to:

in response to determining that the quantum critical point is smaller than a minimum threshold value, iteratively change a design of at least one of the physical elements of the qubit design to obtain a revised qubit design;

form a revised plurality of plaquettes, the revised plurality of plaquettes comprising at least one revised plaquette, representing the at least one changed physical element design of the revised qubit design, each plaquette having at least two ports, each plaquette concatenated to another plaquette via the at least two ports;

obtain a revised representation of the revised qubit design from the revised plurality of plaquettes;

extract a value of inductance (L), a value of capacitance (C) of the revised qubit design and a value of a mutual inductance M between at least one physical element communicatively coupled to the revised qubit design and the revised qubit design;

compute one or more energy scales of the revised qubit design from a quantum modeling environment via the extracted values of L, C and M;

compute a quantum critical point of the revised qubit design; and

determine whether the quantum critical point is greater than a minimum threshold value.

16. The system of claim 15 wherein the at least one non-transitory processor-readable medium communicatively coupleable to the at least one digital processor and that stores at least one processor-executable instruction or data which, when executed by the at least one digital processor, causes the at least one digital processor to change the qubit design to obtain a revised qubit design by adding additional L-tuners, removing L-tuners, changing the design of couplers, and changing a magnitude of an induction coil between the qubit and a first element of a readout.

Assignments (12)
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2025
From: PSPIB UNITAS INVESTMENTS II INC.
To: D-WAVE SYSTEMS INC.; 1372934 B.C. LTD.
Reel/Frame 070470/0098 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Apr 14, 2023
From: D-WAVE SYSTEMS INC.; 1372934 B.C. LTD.
To: PSPIB UNITAS INVESTMENTS II INC., AS COLLATERAL AGENT
Reel/Frame 063340/0888 →
RELEASE OF SECURITY INTEREST Recorded Sep 20, 2022
From: PSPIB UNITAS INVESTMENTS II INC., IN ITS CAPACITY AS COLLATERAL AGENT
To: D-WAVE SYSTEMS INC.
Reel/Frame 061493/0694 →
SECURITY INTEREST Recorded Mar 3, 2022
From: D-WAVE SYSTEMS INC.
To: PSPIB UNITAS INVESTMENTS II INC.
Reel/Frame 059317/0871 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR (REMOVE COMMA) PREVIOUSLY RECORDED ON REEL 057334 FRAME 0606. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 27, 2021
From: D-WAVE SYSTEMS INC.; DWSI HOLDINGS INC.
To: DWSI HOLDINGS INC.
Reel/Frame 057616/0588 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE (REMOVE COMMA) PREVIOUSLY RECORDED ON REEL 057125 FRAME 0427. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 27, 2021
From: MOLAVI, REZA; VOLKMANN, MARK H.; BUNYK, PAUL I.
To: D-WAVE SYSTEMS INC.
Reel/Frame 057616/0568 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR AND ASSIGNEE (REMOVE COMMA) PREVIOUSLY RECORDED ON REEL 057334 FRAME 0609. ASSIGNOR(S) HEREBY CONFIRMS THE CONTINUATION. Recorded Sep 27, 2021
From: D-WAVE SYSTEMS INC.
To: D-WAVE SYSTEMS INC.
Reel/Frame 057616/0585 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE (REMOVE COMMA) PREVIOUSLY RECORDED ON REEL 057302 FRAME 0552. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 27, 2021
From: DWSI HOLDINGS INC.
To: D-WAVE SYSTEMS INC.
Reel/Frame 057616/0628 →
CONTINUATION Recorded Aug 26, 2021
From: D-WAVE SYSTEMS, INC.
To: D-WAVE SYSTEMS, INC.
Reel/Frame 057334/0609 →
MERGER AND CHANGE OF NAME Recorded Aug 26, 2021
From: D-WAVE SYSTEMS, INC.; DWSI HOLDINGS INC.; DWSI HOLDINGS INC.
To: DWSI HOLDINGS INC.
Reel/Frame 057334/0606 →
CHANGE OF NAME Recorded Aug 26, 2021
From: DWSI HOLDINGS INC.
To: D-WAVE SYSTEMS, INC.
Reel/Frame 057302/0552 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 9, 2021
From: MOLAVI, REZA; VOLKMANN, MARK H.; BUNYK, PAUL I.
To: D-WAVE SYSTEMS, INC.
Reel/Frame 057125/0427 →