IP Library Granted Patent US 11,552,090
Granted Patent B2
US 11,552,090 · App. 17/068,470 · Granted Jan 10, 2023

Integrated circuitry comprising a memory array comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

Inventors: Daniel Billingsley (Meridian, ID); Jordan D. Greenlee (Boise, ID); John D. Hopkins (Meridian, ID); Yongjun Jeff Hu (Boise, ID); Swapnil Lengade (Boise, ID)
Assignee: Micron Technology, Inc.
H01L27/11556G11C16/0483H01L27/1157H01L27/11519H01L27/11524H01L27/11565H01L27/11582
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Quick Facts
Patent No.
US 11,552,090
App. No.
17/068,470
Granted
Jan 10, 2023
Kind
B2
Abstract

A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lower-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-second-tiers or a lower of the upper-second-tiers comprises non-stoichiometric silicon dioxide that has a silicon-to-oxygen atomic ratio greater than 0.5. A higher of the upper-second-tiers that is above said lower upper-second-tier comprises silicon dioxide that has a silicon-to-oxygen atomic ratio less than or equal to 0.5. Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-second-tier or said lower upper-second-tier. After the stop, the sacrificial material is removed from the lower channel openings and channel-material strings are formed in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.

Claims (15)

1. A method used in forming a memory array comprising strings of memory cells, comprising:

forming an upper stack directly above a lower stack, the lower stack comprising vertically-alternating lower-first-tiers and lower-second-tiers, the upper stack comprising vertically-alternating upper-first-tiers and upper-second-tiers, lower channel openings extending through the lower-first-tiers and the lower-second-tiers, the lower channel openings having sacrificial material therein;

an upper tier of the lower-second-tiers or a lower tier of the upper-second-tiers comprising non-stoichiometric silicon dioxide having a silicon-to-oxygen atomic ratio greater than 0.5, a higher tier of the upper-second-tiers that is above said lower upper-second-tier comprising silicon dioxide having a silicon-to-oxygen atomic ratio less than or equal to 0.5;

etching upper channel openings through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-second-tier or said lower upper-second-tier; and

after the stop, removing the sacrificial material from the lower channel openings and forming channel-material strings in the upper and lower channel openings.

2. The method of claim 1 wherein the non-stoichiometric silicon dioxide has silicon-to-oxygen atomic ratio no greater than 1.0.

3. The method of claim 1 wherein the upper tier of the lower-second-tiers comprises the non-stoichiometric silicon dioxide.

4. The method of claim 3 wherein the upper tier of the lower-second-tiers is the uppermost tier of the lower-second-tiers.

5. The method of claim 3 wherein multiple of the upper lower-second-tiers comprise the non-stoichiometric silicon dioxide.

6. The method of claim 1 wherein the lower tier of the upper-second-tiers comprises the non-stoichiometric silicon dioxide.

7. The method of claim 6 wherein the lower tier of the upper-second-tiers is the lowest tier of the upper-second-tiers.

8. The method of claim 6 wherein multiple of the lower upper-second-tiers comprise the non-stoichiometric silicon dioxide.

9. The method of claim 1 wherein each of the upper tiers of the lower-second-tiers and the lower tiers of the upper-second-tiers comprises the non-stoichiometric silicon dioxide.

10. The method of claim 1 wherein the etching the upper channel openings to the stop exposes the sacrificial material.

11. The method of claim 1 wherein the etching the upper channel openings to the stop does not expose the sacrificial material, and further comprising thereafter etching through said upper lower-second-tier or said lower upper-second-tier to expose the sacrificial material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 12, 2020
From: BILLINGSLEY, DANIEL; GREENLEE, JORDAN D.; HOPKINS, JOHN D.; HU, YONGJUN JEFF; LENGADE, SWAPNIL
To: MICRON TECHNOLOGY, INC.
Reel/Frame 054030/0205 →
Continuity (2)
Provisional Application 63071563 · Aug 28, 2020
Related Publication 20220068945A1 · Mar 3, 2022