Ultra-low leakage electrostatic discharge device with controllable trigger voltage

1. A electrostatic discharge (ESD) device, comprising:

an input pad;

an underlapped field effect transistor (UL-FET) with a trigger voltage Vt, including:

an underlapped drain region coupled to the input pad;

a source region coupled to ground; and

a gate structure coupled to a first terminal of a capacitor and a second terminal of the capacitor coupled to the input pad;

a blocking layer separating the underlapped drain region from the gate structure of the UL-FET by an underlap distance;

a voltage divider for setting a gate voltage Vg applied to the gate structure of the UL-FET; and

a silicon-controlled-rectifier (SCR) device laterally adjacent the UL-FET, the SCR device including a P-N-P-N configuration, the P-N-P-N configuration including a first portion coupled to the input pad and a second portion coupled to ground.

2. The ESD device according to claim 1 , wherein the voltage divider further comprises the capacitor coupled to the gate structure and the input pad in series with an intrinsic gate-to-source capacitance of the UL-FET.

3. The ESD device according to claim 1 , wherein the UL-FET further comprises a trigger path (TP) formed between the underlapped drain region and the source region.

4. The ESD device according to claim 3 , further comprising a discharge device coupled to the UL-FET for discharging ESD current along a discharge path (DP) from the input pad to ground in response to an ESD event.

5. The ESD device according to claim 1 , wherein the trigger voltage Vt of the UL-FET is controlled by at least one of:

a gate voltage Vg applied to the gate structure;

a capacitance of the capacitor coupled to the gate structure and the input pad; and

the underlap distance between the underlapped drain region and the gate structure.

6. A electrostatic discharge (ESD) device, comprising:

an input pad;

an underlapped n-type field effect transistor (UL-NFET) with a trigger voltage Vt, the UL-NFET including:

an underlapped n+-doped drain region at least partially in a p-type substrate;

an n+-doped source region in the p-type substrate and coupled to ground; and

a gate structure coupled to a first terminal of a capacitor and a second terminal of the capacitor coupled to the input pad;

a silicide blocking layer separating the n+-doped underlapped drain region from the gate structure of the UL-NFET by an underlap distance;

a voltage divider for setting a gate voltage Vg applied to the gate structure of the UL-NFET; and

a silicon-controlled-rectifier (SCR) device laterally adjacent the UL-NFET, the SCR device including:

a p+-doped region coupled to the input pad and over an n-well, the n-well within the p-type substrate,

an n+-doped region over a p-well, the p-well within the p-type substrate and adjacent the n-well, and

an isolation region between the p+-doped region and the n+-doped region.

7. The ESD device according to claim 6 , wherein the voltage divider further comprises the capacitor coupled to the gate structure and the input pad in series with an intrinsic gate-to-source capacitance of the UL-NFET.

8. The ESD device according to claim 6 , wherein the UL-NFET further comprises a trigger path (TP) formed through the p-well between the n+-doped underlapped drain region and the n+-doped source region.

9. The ESD device according to claim 8 , further comprising a discharge device coupled to the UL-NFET for discharging ESD current along a discharge path (DP) from the input pad to ground in response to an ESD event.

10. The ESD device according to claim 6 , wherein the trigger voltage Vt of the UL-NFET is controlled by at least one of:

a gate voltage Vg applied to the gate structure;

a capacitance of the capacitor coupled to the gate structure and the input pad; and

the underlap distance between the n+-doped underlapped drain region and the gate structure.

11. A electrostatic discharge (ESD) device, comprising:

An underlapped n-type field effect transistor (UL-NFET) with a trigger voltage Vt, the UL-NFET including:

an underlapped n+-doped drain region at least partially in a p-type doped substrate;

an n+-doped source region in the p-type substrate and coupled to ground;

a p+-doped region over an n-well, the n-well within the p-type substrate and coupled to ground;

a gate structure coupled to a first terminal of a capacitor and a second terminal of the capacitor coupled to the input pad;

a first silicide blocking layer separating the n+-doped underlapped drain region from the gate structure of the UL-NFET by an underlap distance; and

a voltage divider for setting a gate voltage Vg applied to the gate structure of the UL-NFET; and

a silicon-controlled-rectifier (SCR) device adjacent the UL-NFET, including:

a first p+-doped region over the n-well and adjacent the underlapped n+-doped drain region,

an n+-doped region between the first p+-doped region and a second p+-doped region, wherein the n+-doped region and the second p+-doped region are over a p-well,

a first isolation region between the first p+-doped region and the underlapped n+-doped drain region,

a second isolation region between the first p+-doped region and the n+-doped region, and

a third isolation region between the n+-doped region and the second p+-doped region.

12. The ESD device according to claim 11 , wherein the n+-doped region and the second p+-doped region are coupled to ground.

13. The ESD device according to claim 11 , further including a second silicide blocking layer separating the gate structure and the n+-doped source region.

14. The ESD device according to claim 11 , further including a p+-doped contact in the p-type doped substrate and adjacent the n+-doped source region.

15. The ESD device according to claim 14 , further including a fourth isolation region between the p+-doped contact and the n+-doped source region.

16. The ESD device according to claim 6 , wherein the n+-doped region is coupled to ground.